公开(公告)号：US20170269984A1

公开(公告)日：2017-09-21

申请号：US15075011

申请日：2016-03-18

Applicant: QUALCOMM INCORPORATED

Inventor： ANANTHA IDAPALAPATI ,  AJAYKUMAR SHANKARGOUDA PATIL ,  SUBODH SINGH ,  RAMSWAROOP SOMANI ,  GOPI KRISHNA NEDANURI ,  PAWAN CHHABRA ,  SARBARTHA BANERJEE ,  VICTOR WONG

IPC: G06F11/07 ,  G06F13/24 ,  G06F11/14 ,  G06F13/28

CPC classification number: G06F11/0757 ,  G06F11/0721 ,  G06F11/1441 ,  G06F13/24 ,  G06F13/28

Abstract: Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.

公开(公告)号：US20150261686A1

公开(公告)日：2015-09-17

申请号：US14210512

申请日：2014-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： SANKARAN NAMPOOTHIRI ,  ARUN VALIAPARAMBIL ,  SUBODH SINGH ,  AZZEDINE TOUZNI

IPC: G06F12/10 ,  G06F9/455 ,  G06F11/16 ,  G06F13/28 ,  G06F13/24

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F12/08 ,  G06F13/24 ,  G06F13/28 ,  G06F2009/45575 ,  G06F2009/45583 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/403

Abstract: A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory. A first area of the primary memory is used for storing time critical code and data. A second area is available for demand pages required by a thread executing in the processor. A secondary memory is accessible to a hypervisor. The processor generates an interrupt when a page fault is detected. The hypervisor, in response to the interrupt, initiates a direct memory transfer of information in the secondary memory to the second area available for demand pages in the primary memory. Upon completion of the transfer, the hypervisor communicates a task complete acknowledgement to the processor.

Abstract translation: 便携式计算设备布置有一个或多个子系统，其包括处理器和布​​置成在子系统级操作系统下执行线程的存储器管理单元。 处理器与主存储器通信。 主存储器的第一个区域用于存储时间关键代码和数据。 第二个区域可用于在处理器中执行的线程所需的需求页面。 管理程序可访问辅助内存。 当检测到页面错误时，处理器会产生中断。 管理程序响应于中断，启动将辅助存储器中的信息的直接存储器传送到可用于主存储器中的需求页面的第二区域。 完成传输后，管理程序将任务完成确认通知给处理器。