Architecture to improve write-ability in SRAM

    公开(公告)号:US09721650B1

    公开(公告)日:2017-08-01

    申请号:US15269620

    申请日:2016-09-19

    CPC classification number: G11C11/419 G11C5/025 G11C5/14

    Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

    Access assist with wordline adjustment with tracking cell

    公开(公告)号:US10811088B2

    公开(公告)日:2020-10-20

    申请号:US16299413

    申请日:2019-03-12

    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

    ACCESS ASSIST WITH WORDLINE ADJUSTMENT WITH TRACKING CELL

    公开(公告)号:US20200294580A1

    公开(公告)日:2020-09-17

    申请号:US16299413

    申请日:2019-03-12

    Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

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