公开(公告)号：US11972834B2

公开(公告)日：2024-04-30

申请号：US17774138

申请日：2020-11-09

Applicant: Qualcomm Incorporated

Inventor： Adithya Bhaskaran ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1087 ,  G11C7/1012 ,  G11C7/1084 ,  G11C7/222

Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

公开(公告)号：US10446196B1

公开(公告)日：2019-10-15

申请号：US16164108

申请日：2018-10-18

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Adithya Bhaskaran ,  Sei Seung Yoon

IPC: G11C5/14 ,  G11C11/417

Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.

公开(公告)号：US09928889B1

公开(公告)日：2018-03-27

申请号：US15465239

申请日：2017-03-21

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Rakesh Kumar Sinha ,  Sharad Kumar Gupta ,  Veerabhadra Rao Boda

IPC: G11C11/419 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/06 ,  G06F1/32

CPC classification number: G11C7/12 ,  G06F1/3275 ,  G11C7/062 ,  G11C7/1075 ,  G11C7/14 ,  G11C7/22 ,  G11C7/222 ,  G11C7/227 ,  G11C8/16 ,  G11C11/419

Abstract: A write precharge period for a pseudo-dual-port memory is initiated by an edge (rising or falling) of a read precharge signal. The same edge type (rising or falling) of a write precharge signal signals the end of the write precharge period.

公开(公告)号：US11935606B2

公开(公告)日：2024-03-19

申请号：US17364738

申请日：2021-06-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Sahu ,  Sharad Kumar Gupta ,  Jung Pill Kim ,  Chulmin Jung ,  Jais Abraham

IPC: G11C29/10 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C29/10 ,  G11C7/06 ,  G11C7/106 ,  G11C7/1096

Abstract: A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

公开(公告)号：US20220293148A1

公开(公告)日：2022-09-15

申请号：US17774138

申请日：2020-11-09

Applicant: Qualcomm Incorporated

Inventor： Adithya Bhaskaran ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C7/10 ,  G11C7/22

Abstract: A level-shifting pulse latch is provided for a self-timed memory clock signal for a memory. The level-shifting pulse latch includes a system-power-domain-to-memory-power-domain level-shifter that inverts and level-shifts a system clock signal into an inverted version of the system clock signal. A pass transistor controls whether the inverted version of the system clock signal drives a memory-power-domain latch to produce the self-timed memory clock signal.

公开(公告)号：US09721650B1

公开(公告)日：2017-08-01

申请号：US15269620

申请日：2016-09-19

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Lakshmikantha Holla Vakwadi

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/14

Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

公开(公告)号：US11837313B2

公开(公告)日：2023-12-05

申请号：US17517386

申请日：2021-11-02

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C29/00 ,  G11C29/50 ,  G11C8/08 ,  H03K19/0175 ,  H03K19/20

CPC classification number: G11C29/50016 ,  G11C8/08 ,  G11C2029/5004 ,  H03K19/017509 ,  H03K19/20

Abstract: A memory is provided that is configured to practice a sleep mode without retention in which a both bitcell array and a memory periphery are powered down responsive to an assertion of sleep mode without retention control signal. The sleep mode without retention control signal is also asserted during a DVS scan to power down the bitcell array. The memory includes a power management circuit that responds to an assertion of a DVS scan control signal to prevent the assertion of the sleep mode without retention control signal from causing a power down of the memory periphery during the DVS scan. The memory periphery may thus be thoroughly tested by the DVS scan because leakage current from the bitcell array is prevented by the powering down of the bitcell array.

公开(公告)号：US10811088B2

公开(公告)日：2020-10-20

申请号：US16299413

申请日：2019-03-12

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/419 ,  G11C16/04 ,  G11C16/12 ,  G11C16/08

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

公开(公告)号：US20200294580A1

公开(公告)日：2020-09-17

申请号：US16299413

申请日：2019-03-12

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/419 ,  G11C16/08 ,  G11C16/12 ,  G11C16/04

Abstract: Methods and apparatuses to adjust wordline voltage level are presented. An apparatus includes multiple memory cells arranged in multiple rows. A wordline is configured to couple to one row of the multiple rows for a read or write operation. A wordline driving circuit is configured to provide a voltage level to the wordline to facilitate the read or write operation. A tracking circuit is configured to emulate a characteristic of one of the multiple memory cells. A pull-down circuit is configured to lower the voltage level of the wordline by an amount, based on the tracking circuit, to access the one row of the multiple rows in the read or write operation. A method includes emulating a characteristic of one of multiple of memory cells and lowering a voltage level of the wordline by an amount to access one row of the multiple rows in the read or write operation.

公开(公告)号：US09875790B1

公开(公告)日：2018-01-23

申请号：US15476746

申请日：2017-03-31

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Priyankar Mathuria ,  Sharad Kumar Gupta ,  Lakshmikantha Holla Vakwadi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C7/22 ,  G11C11/417 ,  G11C2207/229

Abstract: A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.