公开(公告)号：US20190181844A1

公开(公告)日：2019-06-13

申请号：US15835861

申请日：2017-12-08

Applicant: QUALCOMM Incorporated

Inventor： Animesh Paul ,  Xinhua Chen

IPC: H03K3/017 ,  H03K5/02

Abstract: In certain aspects, a clock generation circuit couples to a first clock having a first duty cycle and a second clock having the first duty cycle. The second clock lags the first clock by 90 degrees in phase. The clock generation circuit is configured to couple the output terminal to a ground when the first clock and the second clock both are at logic high and decouple the output terminal from the ground when at least one of the first clock and the second clock is at logic low and couple a supply voltage to the output terminal only when the first clock is at logic low and decouple the supply voltage from the output terminal when the first clock is at logic high. The clock generation circuit generates clock signals having a second duty cycle.

公开(公告)号：US09998129B1

公开(公告)日：2018-06-12

申请号：US15711962

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Jingcheng Zhuang ,  Jianyun Hu ,  Animesh Paul ,  Xinhua Chen ,  Frederic Bossu

IPC: H03D3/24 ,  H03L7/18 ,  H03L7/099 ,  H04L7/00 ,  H03L7/197 ,  H04L7/033 ,  H03L7/093

CPC classification number: H03L7/1803 ,  H03C3/0975 ,  H03L7/093 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/18 ,  H03L7/197 ,  H03L7/1976 ,  H04L7/00 ,  H04L7/0008 ,  H04L7/033

Abstract: A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

公开(公告)号：US09973182B2

公开(公告)日：2018-05-15

申请号：US15265217

申请日：2016-09-14

Applicant: QUALCOMM Incorporated

Inventor： Animesh Paul ,  Jingcheng Zhuang ,  Xinhua Chen ,  Ravi Sridhara

IPC: H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K5/156 ,  H03K21/02

CPC classification number: H03K5/1565 ,  H03K21/02

Abstract: Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.