公开(公告)号：US20160254056A1

公开(公告)日：2016-09-01

申请号：US14633793

申请日：2015-02-27

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/18 ,  G11C16/04 ,  G11C17/16

CPC classification number: G11C16/10 ,  G11C16/0466 ,  G11C17/146 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206 ,  H01L29/42348 ,  H01L29/7923

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

Abstract translation: 根据本公开的一些示例的用于一次可编程（OTP）存储器的半导体器件包括栅极，栅极下方的介电区域，介质区域下方的偏移并且偏移到一侧的源极端子，电介质下方的漏极端子 并且偏移到与源极端子相反的一侧，在能够编程半导体器件的电介质区域中的漏极侧电荷阱，以及与漏极侧电荷阱相对的电介质区域中的源极电荷陷阱，并且能够对半导体 设备。

公开(公告)号：US20220230679A1

公开(公告)日：2022-07-21

申请号：US17152564

申请日：2021-01-19

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash MIRHAJ ,  Xiaonan CHEN ,  Ankit SRIVASTAVA ,  Sameer WADHWA ,  Zhongze WANG

IPC: G11C11/419 ,  G06F7/544

Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverters for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line. A write driver controls a power supply voltage to the cross-coupled inverters, the first switch, and the second switch to capacitively write the stored bit to the pair of cross-coupled inverters.

公开(公告)号：US20220108742A1

公开(公告)日：2022-04-07

申请号：US17062148

申请日：2020-10-02

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Zhongze WANG ,  Xiaonan CHEN ,  Xiaochun ZHU

IPC: G11C11/4094 ,  G11C11/4091 ,  G11C11/4099 ,  G11C11/404 ,  G11C5/06

Abstract: Certain aspects of the present disclosure provide a circuit for in-memory computation. The circuit generally includes a memory cell having a bit-line and a complementary bit-line, a first capacitive element coupled to the bit-line, a second capacitive element coupled to the complementary bit-line, a processing circuit, a first switch coupled between a first input of the processing circuit and the bit-line, and a second switch coupled between a second input of the processing circuit and the complementary bit-line

公开(公告)号：US20190156895A1

公开(公告)日：2019-05-23

申请号：US16260026

申请日：2019-01-28

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Xiao LU ,  Xiaonan CHEN ,  Zhongze WANG

IPC: G11C16/10 ,  G11C17/14 ,  H01L27/112 ,  H01L29/792 ,  G11C16/04 ,  G11C17/18 ,  G11C17/16 ,  H01L29/423

Abstract: A semiconductor device for a one-time programmable (OTP) memory according to some examples of the disclosure includes a gate, a dielectric region below the gate, a source terminal below the dielectric region and offset to one side, a drain terminal below the dielectric region and offset to an opposite side from the source terminal, a drain side charge trap in the dielectric region capable of programming the semiconductor device, and a source side charge trap in the dielectric region opposite the drain side charge trap and capable of programming the semiconductor device.

公开(公告)号：US20160268002A1

公开(公告)日：2016-09-15

申请号：US14656699

申请日：2015-03-12

Applicant: QUALCOMM Incorporated

Inventor： Xiaonan CHEN ,  Zhongze WANG ,  Xia LI

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/04 ,  G11C17/12 ,  G11C17/123

Abstract: An OTP memory array includes a plurality of differential P-channel metal oxide semiconductor (PMOS) OTP memory cells programmable and readable in predetermined states of program and read operations, and is capable of providing sufficient margins against global process variations and temperature variations while being compatible with standard logic fin-shaped field effect transistor (FinFET) processes to obviate the need for additional masks and costs associated with additional masks.

Abstract translation: OTP存储器阵列包括在预定的程序和读取操作状态下可编程和可读的多个差分P沟道金属氧化物半导体（PMOS）OTP存储器单元，并且能够在兼容的同时为全局工艺变化和温度变化提供足够的余量 具有标准逻辑鳍状场效应晶体管（FinFET）处理，以避免需要额外的掩模和与附加掩模相关联的成本。

公开(公告)号：US20160155748A1

公开(公告)日：2016-06-02

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jeffrey Junhao XU ,  Zhongze WANG ,  Bin YANG ,  Xiaonan CHEN ,  Yu LU

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，被实现为非易失性存储器件中的铁电偶极子层