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    MEMORY TRAINING
    3.
    发明申请
    MEMORY TRAINING 审中-公开

    公开(公告)号：US20200293415A1

    公开(公告)日：2020-09-17

    申请号：US16354573

    申请日：2019-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Sanku MUKHERJEE ,  Uttkarsh WARDHAN ,  Madan KRISHNAPPA

    IPC: G06F11/22 ,  G06N20/00

    Abstract: Certain aspects of the present disclosure generally relate to memory training. An example method generally includes assigning each of a plurality of data channels of a memory device to at least one processor, performing memory tests, in parallel, on the plurality of data channels by at least in part performing read and write operations on at least two or more of the plurality of data channels in parallel using the at least one processor, and determining a setting for one or more memory interface parameters associated with the memory device relative to a data eye for each of the plurality of data channels determined based on the memory tests.

    TOKEN-BASED POWER-SWITCH CONTROL CIRCUITS
    4.
    发明申请
    TOKEN-BASED POWER-SWITCH CONTROL CIRCUITS 有权
    基于TOKEN的功率开关控制电路

    公开(公告)号：US20160091939A1

    公开(公告)日：2016-03-31

    申请号：US14497258

    申请日：2014-09-25

    Applicant: QUALCOMM Incorporated

    Inventor： Matthew Levi SEVERSON ,  Shih-Hsin Jason HU ,  Dipti Ranjan PAL ,  Madan KRISHNAPPA ,  Jeffrey GEMAR ,  Noman AHMED ,  Mohammad TAMJIDI ,  Mark KEMPFERT

    IPC: G06F1/26

    CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

    Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.

    Abstract translation: 提供一种操作电子设备的方法。 该方法包括接收令牌，激活用于响应于接收到令牌的核心的电源开关，以及基于为核心加电的状态来输出令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 在一个方面，一种电子设备包括配置成提供电源至核心的电源开关。 功率开关控制电路被配置为接收令牌，激活电源开关以响应于接收到令牌来加电核心，基于为核心加电的状态输出接收到的令牌。 接收的令牌的输出被延迟直到达到核心的加电状态。 多个电源开关控制电路被配置为环。

    TEST ARCHITECTURE FOR 3D STACKED CIRCUITS
    5.
    发明公开
    TEST ARCHITECTURE FOR 3D STACKED CIRCUITS 审中-公开

    公开(公告)号：US20230299050A1

    公开(公告)日：2023-09-21

    申请号：US17700329

    申请日：2022-03-21

    Applicant: QUALCOMM Incorporated

    Inventor： Kunal Jain MANGILAL ,  Madan KRISHNAPPA

    IPC: H01L25/065 ,  H01L21/66 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L22/34 ,  H01L22/12 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596

    Abstract: Stacked circuits are configured to facilitate post-stacking testing. According to one example, a stacked circuit may include a first die electrically coupled to a second die through a plurality of interconnects. The first die may include a test input interface configured to receive test data signals and a source test clock signal, a test output interface configured to convey test responses, a first test signal path, at least one first die-to-die output interface configured to convey to the second die the test data signals and a low-latency clock signal received from a low-latency clock path between the test input interface and the at least one first die-to-die output interface, and at least one first die-to-die input interface configured to receive test responses and the clock signal from the second die. Other aspects, embodiments, and features are also included.

    MEMORY REPAIR SYSTEM AND METHOD
    7.
    发明公开
    MEMORY REPAIR SYSTEM AND METHOD 审中-公开

    公开(公告)号：US20240087662A1

    公开(公告)日：2024-03-14

    申请号：US17944691

    申请日：2022-09-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： HONG DAI ,  Amir BOROVIETZKY ,  Arvind JAIN ,  Massine BITAM ,  Madan KRISHNAPPA

    IPC: G11C29/32 ,  G01R31/319 ,  G11C29/44

    CPC classification number: G11C29/32 ,  G01R31/31926 ,  G11C29/44

    Abstract: A system for repairing a random access memory may include serial test interface logic, fuse-sense logic, a repair data register chain, and multiplexing logic. The repair data register chain may include serially interconnected data registers configured to shift data through the repair data register chain. Each data register of the repair data register chain may have a data output configured to be coupled to a repair information input of the random access memory. The multiplexing logic may be configured to provide a soft-repair mode and a hard-repair mode. When the soft-repair mode is selected, the multiplexing logic may be configured to receive soft-repair data provided by the serial test interface logic into the data registers. When the hard-repair mode is selected, the multiplexing logic may be configured to receive the data provided by the fuse-sense logic into the data registers.

    THERMAL MITIGATION OF MULTI-CORE PROCESSOR
    10.
    发明申请
    THERMAL MITIGATION OF MULTI-CORE PROCESSOR 有权
    多核处理器的热减缓

    公开(公告)号：US20160124476A1

    公开(公告)日：2016-05-05

    申请号：US14675409

    申请日：2015-03-31

    Applicant: QUALCOMM Incorporated

    Inventor： Rajat MITTAL ,  Madan KRISHNAPPA ,  Rajit CHANDRA ,  Mohammad TAMJIDI

    IPC: G06F1/20 ,  G06F9/48 ,  G06F1/32 ,  G06F9/50

    CPC classification number: G06F1/324 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/4856 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D10/32

    Abstract: A method, an apparatus, and a computer program product are provided. The apparatus may be a UE. The UE has a processor including a plurality of cores. The plurality of cores includes a first core and remaining cores. The UE determines a temperature of the first core of the plurality of cores. The first core processes a load. The UE determines that the temperature of the first core is greater than a first threshold. The UE determines that the temperature of the first core is not greater than a second threshold. The second threshold is greater than the first threshold. The UE transfers at least a portion of the load of the first core to a second core of the remaining cores in response to determining that the temperature of the first core is greater than the first threshold.

    Abstract translation: 提供了一种方法，装置和计算机程序产品。 该装置可以是UE。 UE具有包括多个核的处理器。 多个芯包括第一芯和剩余芯。 UE确定多个核心的第一核心的温度。 第一个核心处理一个负载。 UE确定第一核心的温度大于第一阈值。 UE确定第一核心的温度不大于第二阈值。 第二阈值大于第一阈值。 响应于确定第一核心的温度大于第一阈值，UE将第一核心的至少一部分负载传送到剩余核心的第二核心。

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