公开(公告)号：US20190288722A1

公开(公告)日：2019-09-19

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti ASURI ,  Krishnaswamy THIAGARAJAN ,  Ashok SWAMINATHAN ,  Shahin MEHDIZAD TALEIE ,  Yen-Wei CHANG ,  Vinod PANIKKATH ,  Sameer Vasantlal VORA ,  Ayush MITTAL ,  Tonmoy BISWAS ,  Sy-Chyuan HWU ,  Zhilong TANG ,  Ibrahim CHAMAS ,  Ping Wing LAI ,  Behnam SEDIGHI ,  Dongwon SEO ,  Nitz SAPUTRA

IPC: H04B1/04 ,  H04B1/00 ,  H04L27/20

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.

公开(公告)号：US20220302883A1

公开(公告)日：2022-09-22

申请号：US17208864

申请日：2021-03-22

Applicant: QUALCOMM Incorporated

Inventor： Ayush MITTAL ,  Sreenivasa MALLIA ,  Arpit GUPTA ,  Krishnaswamy THIAGARAJAN ,  Bhushan Shanti ASURI

IPC: H03F1/42 ,  H03F3/24

Abstract: Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.

公开(公告)号：US20190207558A1

公开(公告)日：2019-07-04

申请号：US15862567

申请日：2018-01-04

Applicant: Qualcomm Incorporated

Inventor： Ayush MITTAL ,  Krishnaswamy THIAGARAJAN ,  Bhushan Shanti ASURI ,  Mahim RANJAN

IPC: H03D7/12

CPC classification number: H03D7/125 ,  H03D2200/0086 ,  H04B1/40

Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.

公开(公告)号：US20180248551A1

公开(公告)日：2018-08-30

申请号：US15441750

申请日：2017-02-24

Applicant: QUALCOMM Incorporated

Inventor： Sreenivasa MALLIA ,  Ayush MITTAL ,  Krishnaswamy THIAGARAJAN ,  Karthikeya ARUPPUKOTTAI BOOMINATHAN

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/018514 ,  H03K19/018528

Abstract: A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components.