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    CLOCK DRIVER FOR TIME-INTERLEAVED DIGITAL-TO-ANALOG CONVERTER
    4.
    发明公开
    CLOCK DRIVER FOR TIME-INTERLEAVED DIGITAL-TO-ANALOG CONVERTER 审中-公开

    公开(公告)号：US20230299757A1

    公开(公告)日：2023-09-21

    申请号：US17654916

    申请日：2022-03-15

    Applicant: QUALCOMM Incorporated

    Inventor： Negar RASHIDI ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN

    IPC: H03K5/05 ,  H03M1/82

    CPC classification number: H03K5/05 ,  H03M1/82

    Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.

    RESISTOR NETWORK WITH ADAPTIVE RESISTANCE FOR DIGITAL-TO-ANALOG CONVERTER (DAC)
    6.
    发明公开
    RESISTOR NETWORK WITH ADAPTIVE RESISTANCE FOR DIGITAL-TO-ANALOG CONVERTER (DAC) 审中-公开

    公开(公告)号：US20230336187A1

    公开(公告)日：2023-10-19

    申请号：US17659531

    申请日：2022-04-18

    Applicant: QUALCOMM Incorporated

    Inventor： Nitz SAPUTRA ,  Ashok SWAMINATHAN

    IPC: H03M1/76 ,  H03K17/687 ,  H03M1/78

    CPC classification number: H03M1/785 ,  H03K17/687 ,  H03M1/76

    Abstract: Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

    RING OSCILLATOR ARCHITECTURE WITH CONTROLLED SENSITIVITY TO SUPPLY VOLTAGE
    7.
    发明申请
    RING OSCILLATOR ARCHITECTURE WITH CONTROLLED SENSITIVITY TO SUPPLY VOLTAGE 有权
    具有控制灵敏度的环形振荡器架构供电电压

    公开(公告)号：US20160336924A1

    公开(公告)日：2016-11-17

    申请号：US14711158

    申请日：2015-05-13

    Applicant: QUALCOMM Incorporated

    Inventor： Xinxin YU ,  Ashok SWAMINATHAN ,  Christian VENERUS

    IPC: H03K3/03

    CPC classification number: H03K3/0315 ,  H03K3/011 ,  H03L7/0995 ,  H03L7/0997

    Abstract: A method and apparatus for controlling a supply sensitivity of a ring oscillator stage are provided. The apparatus is configured to generate, via a voltage biasing module, a first bias signal for a PMOS biasing module based on a supply voltage and a second bias signal for a NMOS biasing module based on the supply voltage, bias, via the PMOS biasing module, triode PMOS degeneration of the inverting module based on the first bias signal, bias, via the NMOS biasing module, triode NMOS degeneration of the inverting module based on the second bias signal, receive an input via an inverting module, and output, via the inverting module, an inverted version of the received input based on the biased triode NMOS degeneration and the biased triode PMOS degeneration.

    Abstract translation: 提供了一种用于控制环形振荡器级的供电灵敏度的方法和装置。 该装置被配置为经由电压偏压模块经由PMOS偏压模块基于供电电压和偏压，基于供电电压和用于NMOS偏置模块的第二偏置信号，经由电压偏压模块产生第一偏置信号 基于第一偏置信号的反相模块的三极管PMOS退化，经由NMOS偏置模块的偏置，基于第二偏置信号的反相模块的三极管NMOS退化，经由反相模块接收输入，并且经由反相模块输出 反相模块，基于偏置三极管NMOS退化和偏置三极管PMOS退化的接收输入的反相形式。

    WIDEBAND CURRENT-MODE LOW-PASS FILTER CIRCUITS
    8.
    发明公开
    WIDEBAND CURRENT-MODE LOW-PASS FILTER CIRCUITS 审中-公开

    公开(公告)号：US20240204753A1

    公开(公告)日：2024-06-20

    申请号：US18068837

    申请日：2022-12-20

    Applicant: QUALCOMM Incorporated

    Inventor： Peter GAZZERRO ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN ,  Osama ELHADIDY ,  Bo YANG

    IPC: H03H11/04 ,  H03M1/06 ,  H03M1/66 ,  H04B1/04

    CPC classification number: H03H11/0461 ,  H03M1/0626 ,  H03M1/66 ,  H04B1/04

    Abstract: Methods and apparatus for filtering a signal using a current-mode filter circuit implementing source degeneration. An example filter circuit generally includes an input node; an output node; a power supply node; a first transistor comprising a drain coupled to the input node; a second transistor comprising a drain coupled to the output node and comprising a gate coupled to a gate of the first transistor; a capacitive element coupled between the drain of the first transistor and the power supply node; a first resistive element coupled between the drain and the gate of the first transistor; a first source degeneration element coupled between a source of the first transistor and the power supply node; and a second source degeneration element coupled between a source of the second transistor and the power supply node.

    COMMON-MODE CURRENT REMOVAL SCHEMES FOR DIGITAL-TO-ANALOG CONVERTERS
    9.
    发明公开
    COMMON-MODE CURRENT REMOVAL SCHEMES FOR DIGITAL-TO-ANALOG CONVERTERS 审中-公开

    公开(公告)号：US20240014824A1

    公开(公告)日：2024-01-11

    申请号：US17811706

    申请日：2022-07-11

    Applicant: QUALCOMM Incorporated

    Inventor： Sumant RAMPRASAD ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN

    IPC: H03M1/08

    CPC classification number: H03M1/08

    Abstract: Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells and having a plurality of shunt branches, and an adjustable resistance circuit coupled between middle nodes of the plurality of shunt branches and a reference potential node for the DAC circuit.

    ADAPTIVE SWITCH BIASING SCHEME FOR DIGITAL-TO-ANALOG CONVERTER (DAC) PERFORMANCE ENHANCEMENT
    10.
    发明申请
    ADAPTIVE SWITCH BIASING SCHEME FOR DIGITAL-TO-ANALOG CONVERTER (DAC) PERFORMANCE ENHANCEMENT 有权

    公开(公告)号：US20210391871A1

    公开(公告)日：2021-12-16

    申请号：US17337619

    申请日：2021-06-03

    Applicant: QUALCOMM Incorporated

    Inventor： Xilin LIU ,  Nitz SAPUTRA ,  Behnam SEDIGHI ,  Ashok SWAMINATHAN ,  Dongwon SEO

    IPC: H03M1/74 ,  G05F3/26 ,  H04B1/04

    Abstract: Methods and apparatus for adaptively generating a reference voltage (VREF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a VREF generation circuit coupled to the regulation circuit and configured to adaptively generate a VREF for the regulation circuit.

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