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公开(公告)号：US09785601B2
公开(公告)日：2017-10-10
申请号：US15045282
申请日：2016-02-17
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
CPC classification number: G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
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公开(公告)号：US08884637B2
公开(公告)日：2014-11-11
申请号：US13900775
申请日：2013-05-23
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
CPC classification number: G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Abstract translation: 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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公开(公告)号：US20160162432A1
公开(公告)日：2016-06-09
申请号：US15045282
申请日：2016-02-17
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Paul D. Bassett , Martin Saint-Laurent
CPC classification number: G06F13/4077 , G06F13/4072 , G06F13/4291 , H03K3/356069 , H03K3/356113 , H03K5/15 , Y02D10/14 , Y02D10/151
Abstract: A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.
Abstract translation: 一种装置包括耦合到第一总线的第一驱动电路，其中第一驱动电路包括第一延迟元件。 第一延迟元件被配置为接收第一输入信号并产生第一输出信号。 当第一输入信号从逻辑高电平转换到逻辑低电平时，第一输出信号在第一延迟周期之后转变逻辑电平。 当第一输入信号从逻辑低电平转换到逻辑高电平时，第一输出信号在第二延迟周期之后转变逻辑电平。 第一延迟元件包括读出放大器。 第一驱动器电路被配置为通过第一总线发送第一输出信号。 该装置还包括被配置为在第二总线上传输第二输出信号的第二驱动器电路。
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公开(公告)号：US20130257466A1
公开(公告)日：2013-10-03
申请号：US13900775
申请日：2013-05-23
Applicant: QUALCOMM Incorporated
Inventor： Baker S. Mohammad , Hong S. Kim , Paul D. Bassett
IPC: G01R31/26
CPC classification number: G01R31/2642 , G11C11/41 , G11C29/12 , G11C29/50
Abstract: In a particular embodiment, a method includes receiving a testing activation signal at a controller coupled to a semiconductor device. The method further includes biasing a well of at least one transistor of the semiconductor device in response to the received testing activation signal. The bias is provided by a biasing circuit that is responsive to the controller. While the well is biased, a test of the semiconductor device is performed to generate testing data.
Abstract translation: 在特定实施例中，一种方法包括在耦合到半导体器件的控制器处接收测试激活信号。 该方法还包括响应于所接收的测试激活信号来偏置半导体器件的至少一个晶体管的阱。 该偏压由对控制器作出响应的偏置电路提供。 当井被偏置时，执行半导体器件的测试以产生测试数据。
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