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公开(公告)号：US10049729B1
公开(公告)日：2018-08-14
申请号：US15708393
申请日：2017-09-19
Applicant: QUALCOMM Incorporated
Inventor： Esin Terzioglu , Sei Seung Yoon , Chulmin Jung , Bin Liang
IPC: G11C11/00 , G11C11/419
Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may change a device operating voltage from a first voltage to a second voltage while the assist circuit is in a first state. The apparatus may also maintain the device operating voltage at the second voltage for a predetermined time. The apparatus may switch the assist circuit from the first state to a second state. The apparatus may adjust the device operating voltage to a third voltage after the predetermined time, wherein the second voltage is a voltage level between the first voltage and the third voltage. By transitioning the device operating voltage from the first voltage to the third voltage while at the same time preventing the assist circuit from entering particular read assist states, the apparatus may reduce a likelihood of read failures.
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公开(公告)号：US20160299517A1
公开(公告)日：2016-10-13
申请号：US14684128
申请日：2015-04-10
Applicant: QUALCOMM Incorporated
Inventor： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
IPC: G05F1/10
Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.
Abstract translation: 公开了电压下降控制。 一种设备包括耦合到外部电源的第一组件和耦合到外部电源的第二组件。 第一组件包括被配置为接收第一电压的第一输入，被配置为响应于对应于第一逻辑值的第一电压由外部电源充电的第一内部电源;以及电压下降控制器，被配置为输出 经由第一输出的第二电压。 响应于满足第二电压电平的第一内部电源的第一电压电平，第二电压对应于第一逻辑值。 第二组件包括被配置为从第一输出接收第二电压的第二输入。
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公开(公告)号：US10133285B2
公开(公告)日：2018-11-20
申请号：US15791226
申请日：2017-10-23
Applicant: QUALCOMM Incorporated
Inventor： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.
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公开(公告)号：US09851730B2
公开(公告)日：2017-12-26
申请号：US14684128
申请日：2015-04-10
Applicant: QUALCOMM Incorporated
Inventor： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.
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公开(公告)号：US11250895B1
公开(公告)日：2022-02-15
申请号：US17089534
申请日：2020-11-04
Applicant: QUALCOMM Incorporated
Inventor： Dhvani Sheth , Anil Chowdary Kota , Hochul Lee , Chulmin Jung , Bin Liang
Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.
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Patent Agency Ranking
公开(公告)号：US20180046209A1
公开(公告)日：2018-02-15
申请号：US15791226
申请日：2017-10-23
Applicant: QUALCOMM Incorporated
Inventor： Sanjay Bhagawan Patil , Daniel Stasiak , Martin Pierre Saint-Laurent , Rui Li , Bin Liang , Sei Seung Yoon , Chulmin Jung
Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.
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公开(公告)号：US11488658B2
公开(公告)日：2022-11-01
申请号：US16862238
申请日：2020-04-29
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Bin Liang , Chi-Jui Chen
IPC: G11C11/4094 , G11C5/02 , G11C7/12 , G11C11/4074 , G11C11/4096
Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.
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公开(公告)号：US11170865B1
公开(公告)日：2021-11-09
申请号：US16868402
申请日：2020-05-06
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Bin Liang , Chi-Jui Chen
Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.
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公开(公告)号：US09978442B2
公开(公告)日：2018-05-22
申请号：US15258964
申请日：2016-09-07
Applicant: QUALCOMM Incorporated
Inventor： Bin Liang , Tony Chung Yiu Kwok , Rui Li , Sei Seung Yoon
IPC: G11C11/4076 , G11C7/14 , G11C11/418 , G11C11/419 , G11C7/10 , G11C13/00
CPC classification number: G11C11/418 , G11C7/1072 , G11C7/227 , G11C8/18 , G11C11/419 , G11C13/0061
Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.
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公开(公告)号：US20210343330A1
公开(公告)日：2021-11-04
申请号：US16862238
申请日：2020-04-29
Applicant: QUALCOMM Incorporated
Inventor： Chulmin Jung , Bin Liang , Chi-Jui Chen
IPC: G11C11/4094 , G11C11/4074 , G11C11/4096 , G11C7/12 , G11C5/02
Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.
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