公开(公告)号：US11894050B2

公开(公告)日：2024-02-06

申请号：US17481601

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Dhvani Sheth ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：US11854609B2

公开(公告)日：2023-12-26

申请号：US17446195

申请日：2021-08-27

Applicant: QUALCOMM Incorporated

Inventor： Arun Babu Pallerla ,  Anil Chowdary Kota ,  Hochul Lee

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory is provided that includes multiple memory banks, each one of the memory banks being associated with a read multiplexer. A first read multiplexer couples a first plurality of bit lines to a first sense node pair, and a second read multiplexer couples a second plurality of bit lines to a second sense node pair. A first sense amplifier is coupled to the first sense node pair. The second sense node pair may be coupled to the same sense amplifier or a different sense amplifier.

公开(公告)号：US10796735B1

公开(公告)日：2020-10-06

申请号：US16459320

申请日：2019-07-01

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Keejong Kim ,  Anil Chowdary Kota ,  Chulmin Jung

IPC: G11C7/22 ,  G11C7/08 ,  G11C7/12 ,  G11C7/14 ,  G11C7/00 ,  G11C7/06

Abstract: In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.

公开(公告)号：US10483457B1

公开(公告)日：2019-11-19

申请号：US16102941

申请日：2018-08-14

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/04 ,  H01L27/22 ,  H01L43/06 ,  G11C11/56 ,  G11C11/18 ,  G11C11/16

Abstract: Aspects of the disclosure provide magnetoresistive random access memory (MRAM) and methods. The MRAM generally includes a first magnetic tunnel junction (MTJ) storage element comprising a first fixed layer, a first insulating layer, and a first free layer, and a second MTJ storage element comprising a second fixed layer, a second insulating layer, and a second free layer. The MRAM further includes a conductive layer connected to a source line, first bit line, and a second bit line, wherein the first MTJ storage element is disposed above and connected to the conductive layer and the first bit line at a first end and connected to the first bit line at a second end, and wherein the second MTJ storage element is disposed above and connected to the conductive layer and the second bit line at a first end and connected to the second bit line at a second end.

公开(公告)号：US11250924B1

公开(公告)日：2022-02-15

申请号：US17075002

申请日：2020-10-20

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Anne Srikanth

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.

公开(公告)号：US11250895B1

公开(公告)日：2022-02-15

申请号：US17089534

申请日：2020-11-04

Applicant: QUALCOMM Incorporated

Inventor： Dhvani Sheth ,  Anil Chowdary Kota ,  Hochul Lee ,  Chulmin Jung ,  Bin Liang

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/30 ,  G11C7/10

Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.

公开(公告)号：US11222706B1

公开(公告)日：2022-01-11

申请号：US17075002

申请日：2020-10-20

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Anne Srikanth

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: An OTP memory cell circuit includes a read access switch coupled to a fuse in a read current path to allow a read current to flow through the fuse during a read operation. The read access switch, which can be shut off in a write operation, is sized according to the read current to reduce leakage currents that can cause unreliable results. A diode circuit coupled to a node between the read access switch and the fuse provides a write current path through the fuse different from the read current path in the OTP memory cell circuit. The diode circuit is configured to drive, through the write current path including the fuse, a write current sufficient to blow the fuse in a write operation. The diode circuit occupies a smaller area than a write access transistor of comparable drive strength in the OTP memory cell circuit.

公开(公告)号：US11114176B1

公开(公告)日：2021-09-07

申请号：US16811145

申请日：2020-03-06

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Keejong Kim

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

公开(公告)号：US10460785B1

公开(公告)日：2019-10-29

申请号：US16011866

申请日：2018-06-19

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Chando Park ,  Seung Hyuk Kang

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  G11C11/18 ,  G11C11/02

Abstract: A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.

公开(公告)号：US11568904B1

公开(公告)日：2023-01-31

申请号：US17451110

申请日：2021-10-15

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

Abstract: A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.