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公开(公告)号:US11959962B2
公开(公告)日:2024-04-16
申请号:US17808357
申请日:2022-06-23
Applicant: QUALCOMM Incorporated
Inventor: Chengyue Yu , Hua Guan , Yingjie Chen , Fan Yang , Yufei Pan , Jize Jiang , Shamim Ahmed
IPC: G01R31/28
CPC classification number: G01R31/2896 , G01R31/2853 , G01R31/2891
Abstract: Apparatus and techniques for an integrated circuit (IC) package to automatically detect, through an input/out pin, external component parameters and parasitics. An example IC package generally includes a pin for coupling to a component external to the IC package, and at least one of a resistance detector, an inductance detector, or a capacitance detector coupled to the pin, and configured to detect at least one of a resistance, an inductance, or a capacitance, respectively, of a lumped parameter model for the component external to the IC package. The resistance detector, inductance detector, or capacitance detector may also be configured to detect parasitics associated with at least one of the component, the pin, or a connection between the component and the pin.
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公开(公告)号:US11601051B2
公开(公告)日:2023-03-07
申请号:US16444844
申请日:2019-06-18
Applicant: QUALCOMM Incorporated
Inventor: Chengyue Yu , Zhen Ning Low , Guoyong Guo , Jiwei Chen
Abstract: Certain aspects of the present disclosure generally relate to a connection terminal pattern and layout for a three-level buck regulator. One example electronic module generally includes a substrate, an integrated circuit (IC) package disposed on the substrate and comprising transistors of a three-level buck regulator, a capacitive element of the three-level buck regulator disposed on the substrate, and an inductive element of the three-level buck regulator disposed on the substrate. In certain aspects, the capacitive element and the inductive element may be disposed adjacent to different sides of the IC package.
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