公开(公告)号：US10191526B2

公开(公告)日：2019-01-29

申请号：US15345871

申请日：2016-11-08

Applicant: QUALCOMM Incorporated

Inventor： Madjid Hafizi ,  Chiu Keung Tang

IPC: G06F1/26 ,  G06F1/32 ,  H03K19/003 ,  H03K19/0175

Abstract: A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differential transistors, and a current source coupled in series between the output terminals and a lower voltage rail. The transmit driver includes a first bias voltage generator configured to generate a first bias voltage based on the supply voltage across the output differential terminals. The first bias voltage is applied to the control terminals of the first pair of over-voltage protection transistors. The transmit driver includes a second bias generator for generating a second (substantially fixed) bias voltage for the control terminals of the second pair of over-voltage protection transistors. The transmit driver may be configured to operate based on a 3.3V supply voltage provided by an HDMI sink, or based on a 1.8V supply voltage provided by a bridge chip.

公开(公告)号：US11711077B1

公开(公告)日：2023-07-25

申请号：US17805211

申请日：2022-06-02

Applicant: QUALCOMM Incorporated

Inventor： Chiu Keung Tang ,  Zhiqin Chen

IPC: G11C7/06 ,  H03K17/687 ,  G11C27/02 ,  H03K19/20

CPC classification number: H03K17/6872 ,  G11C7/06 ,  G11C27/02 ,  H03K17/6874 ,  H03K19/20

Abstract: A regeneration circuit includes a first inverting circuit and a second inverting circuit. The regeneration circuit also includes a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit, a third transistor and a fourth transistor. A gate of the first transistor and a gate of the fourth transistor are coupled to a first input, and a gate of the second transistor and a gate of the fourth transistor are coupled to a second input. The regeneration circuit further includes a first switch and a second switch. The first switch and the third transistor are coupled in series between a first rail and the first transistor, and the second switch and the fourth transistor are coupled in series between the first rail and the second transistor.

公开(公告)号：US20180129256A1

公开(公告)日：2018-05-10

申请号：US15345871

申请日：2016-11-08

Applicant: QUALCOMM Incorporated

Inventor： Madjid Hafizi ,  Chiu Keung Tang

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/266 ,  G06F1/3296 ,  H03K19/00315 ,  H03K19/017509

Abstract: A transmit driver is configured to operate under distinct supply voltage provided at output differential terminals. The transmit driver includes differential input transistors, first and second pairs of over-voltage protection differential transistors, and a current source coupled in series between the output terminals and a lower voltage rail. The transmit driver includes a first bias voltage generator configured to generate a first bias voltage based on the supply voltage across the output differential terminals. The first bias voltage is applied to the control terminals of the first pair of over-voltage protection transistors. The transmit driver includes a second bias generator for generating a second (substantially fixed) bias voltage for the control terminals of the second pair of over-voltage protection transistors. The transmit driver may be configured to operate based on a 3.3V supply voltage provided by an HDMI sink, or based on a 1.8V supply voltage provided by a bridge chip.

公开(公告)号：US12009811B2

公开(公告)日：2024-06-11

申请号：US18327832

申请日：2023-06-01

Applicant: QUALCOMM Incorporated

Inventor： Chiu Keung Tang ,  Zhiqin Chen

IPC: G11C7/06 ,  G11C27/02 ,  H03K17/687 ,  H03K19/20

CPC classification number: H03K17/6872 ,  G11C7/06 ,  G11C27/02 ,  H03K17/6874 ,  H03K19/20

Abstract: A regeneration circuit includes a first inverting circuit, a second inverting circuit, a first transistor coupled to an input of the second inverting circuit, and a second transistor coupled to an input of the first inverting circuit. The regeneration circuit also includes a third transistor including a gate coupled to a gate of the first transistor, a first switch configured to couple the third transistor to the input of the second inverting circuit based on a voltage of the first inverting circuit, a fourth transistor including a gate coupled to a gate of the second transistor, and a second switch configured to couple the fourth transistor to the input of the first inverting circuit based on a voltage of the second inverting circuit.

公开(公告)号：US11329639B1

公开(公告)日：2022-05-10

申请号：US17212366

申请日：2021-03-25

Applicant: QUALCOMM Incorporated

Inventor： Chiu Keung Tang ,  Zhiqin Chen

IPC: H03K5/13 ,  H03K5/156 ,  H03K5/00

Abstract: A novel delay circuit for quadrature clock generation with insensitivity to process, voltage, temperature (PVT) variations and equal rising/falling edges is disclosed. In one implementation, the delay circuit includes a first N-substage having a sinking current source, configured to receive an input signal and to generate a rising edge of an output signal of the delay circuit, wherein the output signal is a delayed version of the input signal. The delay circuit further includes a first P-substage having a sourcing current source, configured to receive the input signal and to generate a falling edge of the output signal, where the sinking current source and the sourcing current source are variable in response to respective ones of a plurality of bias voltages.