公开(公告)号：US11221971B2

公开(公告)日：2022-01-11

申请号：US15274665

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Derek Hower ,  Harold Wade Cain, III ,  Carl Alan Waldspurger

IPC: G06F13/16 ,  G06F12/0811 ,  G06F9/54

Abstract: Systems and methods are directed to managing access to a shared memory. A request received at a memory controller, for access to the shared memory from a client of one or more clients configured to access the shared memory, is placed in at least one queue in the memory controller. A series of one or more timeout values is assigned to the request, based, at least in part on a priority associated with the client which generated the request. The priority may be fixed or based on a Quality-of-Service (QoS) class of the client. A timer is incremented while the request remains in the first queue. As the timer traverses each one of the one or more timeout values in the series, a criticality level of the request is incremented. A request with a higher criticality level may be prioritized for servicing over a request with a lower criticality level.

公开(公告)号：US10379863B2

公开(公告)日：2019-08-13

申请号：US15712119

申请日：2017-09-21

Applicant: QUALCOMM Incorporated

Inventor： Shivam Priyadarshi ,  Rami Mohammad A. Al Sheikh ,  Brandon Dwiel ,  Derek Hower

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: Systems and methods for constructing an instruction slice for prefetching data of a data-dependent load instruction include a slicer for identifying a load instruction in an instruction sequence as a first occurrence of a qualified load instruction which will miss in a last-level cache. A commit buffer stores information pertaining to the first occurrence of the qualified load instruction and shadow instructions which follow. For a second occurrence of the qualified load instruction, an instruction slice is constructed from the information in the commit buffer to form a slice payload. A pre-execution engine pre-executes the instruction slice based on the slice payload to determine an address from which data is to be fetched for execution of a third and any subsequent occurrences of the qualified load instruction. The data is prefetched from the determined address for the third and any subsequent occurrence of the qualified load instruction.

公开(公告)号：US10303608B2

公开(公告)日：2019-05-28

申请号：US15683391

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad Al Sheikh ,  Shivam Priyadarshi ,  Brandon Dwiel ,  David John Palframan ,  Derek Hower ,  Muntaquim Faruk Chowdhury

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1045 ,  G06F12/109 ,  G06F9/345 ,  G06F9/38

Abstract: A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual address is computed based on the delta value and the first virtual address. Data associated with the second virtual address is then prefetched from a main memory to the data cache prior to a second load instruction specifying the second virtual address missing in the data cache.