公开(公告)号：US10956645B2

公开(公告)日：2021-03-23

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  G06F30/394 ,  G06F30/39 ,  G06F30/327 ,  G06F30/392 ,  G06F30/398 ,  H01L23/522 ,  H01L23/528 ,  G06F115/08 ,  G06F119/06

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

公开(公告)号：US20180144086A1

公开(公告)日：2018-05-24

申请号：US15432431

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.

公开(公告)号：US11476186B2

公开(公告)日：2022-10-18

申请号：US17081720

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Ramaprasath Vilangudipitchai ,  Gudoor Reddy ,  Samrat Sinharoy ,  Smeeta Heggond ,  Anil Kumar Koduru ,  Kamesh Medisetti ,  Seung Hyuk Kang

IPC: H01L23/522 ,  H01L27/02

Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

公开(公告)号：US20190220571A1

公开(公告)日：2019-07-18

申请号：US16366918

申请日：2019-03-27

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: G06F17/50 ,  H01L23/528 ,  H01L23/522

CPC classification number: G06F17/5077 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/66 ,  G06F2217/78 ,  H01L23/5226 ,  H01L23/5286

Abstract: The place and route stage for a hard macro is modified to assign a more robust power-grid tier to a critical path for a hard macro and to assign a less robust power-grid tier to a remainder of the hard macro.

公开(公告)号：US10318694B2

公开(公告)日：2019-06-11

申请号：US15432431

申请日：2017-02-14

Applicant: QUALCOMM Incorporated

Inventor： Joon Hyung Chung ,  Mikhail Popovich ,  Gudoor Reddy

IPC: H01L23/48 ,  H01L29/40 ,  H01L23/50 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528

Abstract: The place and route stage for a hard macro including a plurality of tiles is modified so that some of the tiles are assigned a more robust power-grid tier and so that others ones of the tiles are assigned a less robust power-grid tier.