中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.016 seconds)

    SHARED MEMORY ARCHITECTURE FOR A NEURAL SIMULATOR
    1.
    发明申请
    SHARED MEMORY ARCHITECTURE FOR A NEURAL SIMULATOR 审中-公开
    用于神经模拟器的共享存储器架构

    公开(公告)号：US20150106317A1

    公开(公告)日：2015-04-16

    申请号：US14451954

    申请日：2014-08-05

    Applicant: QUALCOMM Incorporated

    Inventor： Venkat Rangan ,  Jan Krzys Wegrzyn ,  Jeffrey Alexander Levin ,  John Paul Daniels

    IPC: G06N3/10 ,  G06F12/02

    CPC classification number: G06F12/02 ,  G06N3/049 ,  G06N3/063

    Abstract: Aspects of the present disclosure provide methods and apparatus for allocating memory in an artificial nervous system simulator implemented in hardware. According to certain aspects, memory resource requirements for one or more components of an artificial nervous system being simulated may be determined and portions of a shared memory pool (which may include on-chip and/or off-chip RAM) may be allocated to the components based on the determination.

    Abstract translation: 本公开的方面提供了在硬件中实现的人造神经系统模拟器中分配存储器的方法和装置。 根据某些方面，可以确定正在模拟的人造神经系统的一个或多个组件的存储器资源需求，并且可以将共享存储器池（其可以包括片上和/或片外RAM）的部分分配给 组件基于确定。

    Efficient hardware implementation of spiking networks
    2.
    发明授权
    Efficient hardware implementation of spiking networks 有权
    高效的硬件实现spiking网络

    公开(公告)号：US09542643B2

    公开(公告)日：2017-01-10

    申请号：US14267005

    申请日：2014-05-01

    Applicant: QUALCOMM Incorporated

    Inventor： Jeffrey Alexander Levin ,  Venkat Rangan ,  Erik Christopher Malone

    IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/08

    Abstract: Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.

    Abstract translation: 本公开的某些方面支持在人造神经系统中同时操作多个超级神经元处理单元，其中将多个人造神经元分配给每个超级神经元处理单元。 超神经元处理单元可以与用于存储和加载人造神经系统的突触权重和可塑性参数的存储器接口，其中存储器的组织允许连续的存储器访问。

    Post ghost plasticity
    6.
    发明授权
    Post ghost plasticity 有权
    后鬼可塑性

    公开(公告)号：US09418332B2

    公开(公告)日：2016-08-16

    申请号：US14167752

    申请日：2014-01-29

    Applicant: QUALCOMM Incorporated ,  Nina Marcos

    Inventor： Jason Frank Hunzinger ,  Jeffrey Alexander Levin

    IPC: G06F15/18 ,  G06N3/08 ,  G06N3/04

    CPC classification number: G06N3/049 ,  G06N3/04

    Abstract: Methods and apparatus are provided for inferring and accounting for missing post-synaptic events (e.g., a post-synaptic spike that is not associated with any pre-synaptic spikes) at an artificial neuron and adjusting spike-timing dependent plasticity (STDP) accordingly. One example method generally includes receiving, at an artificial neuron, a plurality of pre-synaptic spikes associated with a synapse, tracking a plurality of post-synaptic spikes output by the artificial neuron, and determining at least one of the post-synaptic spikes is associated with none of the plurality of pre-synaptic spikes. According to certain aspects, determining inferring missing post-synaptic events may be accomplished by using a flag, counter, or other variable that is updated on post-synaptic firings. If this post-ghost variable changes between pre-synaptic-triggered adjustments, then the artificial nervous system can determine there was a missing post-synaptic pairing.

    Abstract translation: 提供了用于推断和计算在人造神经元处丢失的突触后事件（例如，与突触前尖峰之间不相关的突触后尖峰）并相应地调整尖峰时序依赖性可塑性（STDP）的方法和装置。 一个示例性方法通常包括在人造神经元处接收与突触相关联的多个突触前尖峰，跟踪由人造神经元输出的多个突触后尖峰，并且确定突触后尖峰中的至少一个是 与多个突触前尖峰中的任一个相关联。 根据某些方面，确定推断缺失的突触后事件可以通过使用在突触后发射上更新的标志，计数器或其他变量来实现。 如果这个后幽灵变量在突触前触发的调整之间变化，则人造神经系统可以确定缺少突触后配对。

Patent Agency Ranking