公开(公告)号：US20180123538A1

公开(公告)日：2018-05-03

申请号：US15583890

申请日：2017-05-01

Applicant: QUALCOMM Incorporated

Inventor： Jiang CHEN ,  Jeremy GOLDBLATT ,  Jose CABANILLAS

IPC: H03G3/30 ,  H03F3/193 ,  H03F3/21 ,  H03F1/56

CPC classification number: H03G3/3042 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/32 ,  H03F1/56 ,  H03F3/189 ,  H03F3/193 ,  H03F3/21 ,  H03F3/245 ,  H03F3/45179 ,  H03F3/505 ,  H03F2200/102 ,  H03F2200/211 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/537 ,  H03F2200/69 ,  H03F2203/45394 ,  H03G2201/106

Abstract: A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.