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公开(公告)号：US10965442B2
公开(公告)日：2021-03-30
申请号：US16150123
申请日：2018-10-02
Applicant: QUALCOMM Incorporated
Inventor： Eskinder Hailu , Bupesh Pandita , Jon Boyette , Hadi Goudarzi , Yong Suk Jun , Zhi Zhu , Minhan Chen
Abstract: A receiver is provided that includes a time-to-digital converter for converting a phase difference between a clock signal and a received data signal into a phase-difference digital code. The receiver also includes a logic circuit that controls a programmable delay line to delay the clock signal into a delayed clock signal by a delay that is responsive to a difference between the phase-difference code and a unit interval for the clock signal. The delayed clock signal clocks a flip-flop to register the received data signal.
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公开(公告)号：US20190007053A1
公开(公告)日：2019-01-03
申请号：US16017308
申请日：2018-06-25
Applicant: QUALCOMM Incorporated
Inventor： Eskinder Hailu , Bupesh Pandita , Jon Boyette
CPC classification number: H03L7/0807 , H03L7/0802 , H03L7/0812 , H03L7/095 , H03M9/00 , H04B1/16 , H04L7/033
Abstract: A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.
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公开(公告)号：US10389366B2
公开(公告)日：2019-08-20
申请号：US16017308
申请日：2018-06-25
Applicant: QUALCOMM Incorporated
Inventor： Eskinder Hailu , Bupesh Pandita , Jon Boyette
Abstract: A gear-shifting serializer-deserializer (SerDes) is provided that uses a first divisor value to form a divided clock while de-serializing a serial data stream prior to a lock detection and that uses a second divisor value to form the divided clock value after the lock detection, wherein the second divisor value is greater than the first divisor value.
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