公开(公告)号：US12009295B2

公开(公告)日：2024-06-11

申请号：US17454203

申请日：2021-11-09

Applicant: QUALCOMM Incorporated

Inventor： Thomas Hua-Min Williams ,  Matthew Chauncey Kusbit ,  Luis Chen ,  Keyurkumar Karsanbhai Kansagra ,  Smeeta Heggond

IPC: H01L21/00 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L27/092

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

公开(公告)号：US11687106B1

公开(公告)日：2023-06-27

申请号：US17662460

申请日：2022-05-09

Applicant: QUALCOMM Incorporated

Inventor： Giby Samson ,  Harshat Pant ,  Keyurkumar Karsanbhai Kansagra ,  Mohammed Yousuff Shariff ,  Vinayak Nana Mehetre

IPC: G05F1/56 ,  G06F1/26 ,  H03K17/687

CPC classification number: G05F1/56 ,  G06F1/263 ,  H03K17/687

Abstract: A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

公开(公告)号：US20230141245A1

公开(公告)日：2023-05-11

申请号：US17454203

申请日：2021-11-09

Applicant: QUALCOMM Incorporated

Inventor： Thomas Hua-Min Williams ,  Matthew Chauncey Kusbit ,  Luis Chen ,  Keyurkumar Karsanbhai Kansagra ,  Smeeta Heggond

IPC: H01L23/528 ,  H01L27/092

CPC classification number: H01L23/528 ,  H01L27/092

Abstract: An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.