公开(公告)号：US20240203376A1

公开(公告)日：2024-06-20

申请号：US18066034

申请日：2022-12-14

Applicant: QUALCOMM Incorporated

Inventor： Sreekanth Modaikkal ,  Kumar Saurabh ,  Gary Arthur Ciambella ,  Chun Wang ,  Anitha Madugiri Siddaraju

IPC: G09G5/14 ,  G06T1/60 ,  G09G5/397

CPC classification number: G09G5/14 ,  G06T1/60 ,  G09G5/397 ,  G09G2340/10 ,  G09G2340/12

Abstract: Efficiently processing multiple non-overlapping layer images in display processing units is disclosed herein. In this regard, in some exemplary aspects, a display processing unit comprising a plurality of memory access pipeline circuits and a layer mixer circuit is provided. For each non-overlapping layer image of a plurality of non-overlapping layer images, a memory access pipeline circuit obtains image configuration data for the non-overlapping layer image, and fetches the non-overlapping layer image from an image data storage device based on the image configuration data. The memory access pipeline circuit then outputs each pixel of the non-overlapping layer image as part of an intermediate preblend image data stream based on the image configuration data. The layer mixer circuit blends the intermediate preblend image data stream and a background layer image data stream comprising a background layer image as a display data stream, and outputs the display data stream to a display device.

公开(公告)号：US11978372B1

公开(公告)日：2024-05-07

申请号：US18318646

申请日：2023-05-16

Applicant: QUALCOMM Incorporated

Inventor： Sreekanth Modaikkal ,  Kumar Saurabh ,  Kalyan Thota ,  Vishnuvardhan Prodduturi ,  Chun Wang

IPC: G09G3/00 ,  G06F3/01 ,  G06F3/14 ,  G09G5/12

CPC classification number: G09G3/002 ,  G06F3/011 ,  G06F3/1423 ,  G09G5/12 ,  G06F2203/01

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for synchronized dual eye variable refresh rate update for a VR display. A display processor obtains an indication of a synchronous flush or an asynchronous flush with respect to a first DPU and/or a second DPU. The display processor determines whether a first flush operation and/or a second flush operation is available at a time instance, where the first flush operation and the second flush operation are associated with the first DPU and/or the second DPU. The display processor performs, based on a VSync instance, the first flush operation and/or the second flush operation based on whether the first flush operation and/or the second flush operation are available at the time instance and based on the indication of the synchronous flush or the asynchronous flush.

公开(公告)号：US09990690B2

公开(公告)日：2018-06-05

申请号：US14860225

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Kumar Saurabh ,  Sreekanth Modaikkal ,  Anitha Madugiri Siddaraju ,  Naveenchandra Shetty Brahmavar

IPC: G09G5/39 ,  G06T1/60 ,  G09G5/399 ,  G09G3/20

CPC classification number: G06T1/60 ,  G09G3/20 ,  G09G5/399 ,  G09G2350/00 ,  G09G2360/122 ,  G09G2360/18

Abstract: In an example, a method for tile-based processing by a display processor may include reading first foreground tile data of a foreground image from a first memory space. The method may include storing the read first foreground tile data into a second memory space. The method may include reading first background tile data of a background image from the first memory space. The method may include storing the read first background tile data into a third memory space. The method may include reading a subset of data of the first foreground tile data from the second memory space. The method may include reading a subset of data of the first background tile data from the third memory space.

公开(公告)号：US20170083999A1

公开(公告)日：2017-03-23

申请号：US14860225

申请日：2015-09-21

Applicant: QUALCOMM Incorporated

Inventor： Kumar Saurabh ,  Sreekanth Modaikkal ,  Anitha Madugiri Siddaraju ,  Naveenchandra Shetty Brahmavar

IPC: G06T1/60 ,  G09G5/399 ,  G06T1/20

CPC classification number: G06T1/60 ,  G09G3/20 ,  G09G5/399 ,  G09G2350/00 ,  G09G2360/122 ,  G09G2360/18

Abstract: In an example, a method for tile-based processing by a display processor may include reading first foreground tile data of a foreground image from a first memory space. The method may include storing the read first foreground tile data into a second memory space. The method may include reading first background tile data of a background image from the first memory space. The method may include storing the read first background tile data into a third memory space. The method may include reading a subset of data of the first foreground tile data from the second memory space. The method may include reading a subset of data of the first background tile data from the third memory space.

公开(公告)号：US12100335B2

公开(公告)日：2024-09-24

申请号：US18056649

申请日：2022-11-17

Applicant: QUALCOMM Incorporated

Inventor： Chun Wang ,  Sreekanth Modaikkal ,  Kumar Saurabh ,  Samson Kim ,  Kit Fong Ng

IPC: G09G3/20 ,  G09G3/00 ,  G09G5/391

CPC classification number: G09G3/2096 ,  G09G3/001 ,  G09G5/391 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2340/0407 ,  G09G2360/06 ,  G09G2360/08 ,  G09G2370/10 ,  G09G2370/16

Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for a power efficient display architecture. A display processor may obtain an indication that UC is to be displayed at a first resolution or a second resolution, where the first resolution is higher than the second resolution. The display processor may drive a first display via a first controller of a first DPU based on the indication. The display processor may drive a second display via a controller of a second DPU if the UC is to be displayed at the first resolution, or drive the second display via a second controller of the first DPU if the UC is to be displayed at the second resolution.