公开(公告)号：US20250096051A1

公开(公告)日：2025-03-20

申请号：US18471069

申请日：2023-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jaehyun YEON ,  Kun FANG ,  Suhyung HWANG ,  Sang-Jae LEE ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Zhijie WANG ,  Seongho KIM

IPC: H01L23/13 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/16

Abstract: A package comprising a first substrate; a first integrated device coupled to the first substrate through at least a first plurality of solder interconnects; a second substrate coupled to the first substrate through at least a second plurality of solder interconnects, wherein the second substrate includes a cavity; and an encapsulation layer located at least between the first substrate and the second substrate, wherein the encapsulation layer is coupled to the first substrate, the second substrate and the first integrated device.

公开(公告)号：US20230078231A1

公开(公告)日：2023-03-16

申请号：US17476383

申请日：2021-09-15

Applicant: QUALCOMM Incorporated

Inventor： Kun FANG ,  Jaehyun YEON ,  Suhyung HWANG ,  Hyunchul CHO

IPC: H01L23/498 ,  H01L21/48

Abstract: A package that includes a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer and a plurality of interconnects comprising a first via interconnect and a first trace interconnect, wherein the first via interconnect is directly coupled to the first trace interconnect. The first via interconnect is coupled to the first trace interconnect without an intervening pad interconnect between the first via interconnect and the first trace interconnect.

公开(公告)号：US20220310488A1

公开(公告)日：2022-09-29

申请号：US17210314

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Kun FANG ,  Jaehyun YEON ,  Suhyung HWANG ,  Hong Bok WE

IPC: H01L23/482 ,  H01L23/522 ,  H01L23/528

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate comprises at least one dielectric layer; a plurality of interconnects comprising plurality of pad-on-pad interconnects, wherein the plurality of pad-on-pad interconnects is embedded through a first surface of the substrate. The plurality of pad-on-pad interconnects includes a first pad-on-pad interconnect comprising a first pad and a second pad coupled to the first pad. The package further comprising a solder resist layer located over the first surface of the substrate. The solder resist layer comprises a first solder resist layer portion comprising a first thickness; and a second solder resist layer portion comprising a second thickness that is less than the first thickness. The second solder resist layer portion is located between the at least one dielectric layer and the integrated device.

公开(公告)号：US20220115312A1

公开(公告)日：2022-04-14

申请号：US17066318

申请日：2020-10-08

Applicant: QUALCOMM Incorporated

Inventor： Kun FANG ,  Jaehyun YEON ,  Suhyung HWANG ,  Hong Bok WE

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A substrate that includes a core layer, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, a plurality of first interconnects located over a surface of the at least one first dielectric layer, a plurality of second interconnects located over the surface of the at least one first dielectric layer, a plurality of third interconnects located over the surface of the at least one first dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. The plurality of third interconnects and the plurality of second interconnects are co-planar to the plurality of first interconnects. The solder resist layer includes a first portion, a second portion, and a third portion.

公开(公告)号：US20230093681A1

公开(公告)日：2023-03-23

申请号：US17479691

申请日：2021-09-20

Applicant: QUALCOMM Incorporated

Inventor： Hyunchul CHO ,  Kun FANG ,  Jaehyun YEON ,  Suhyung HWANG

IPC: H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00

Abstract: A package that includes a substrate, a first integrated device coupled to a first surface of the substrate, and a second integrated device coupled to a second surface of the substrate. The substrate includes at least one dielectric layer, a first plurality of high-density interconnects located in the at least one dielectric layer and through a first surface of the at least one dielectric layer; a second plurality of high-density interconnects located in the at least one dielectric.

公开(公告)号：US20220068662A1

公开(公告)日：2022-03-03

申请号：US17010693

申请日：2020-09-02

Applicant: QUALCOMM Incorporated

Inventor： Kun FANG ,  Jaehyun YEON ,  Suhyung HWANG ,  Hong Bok WE

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.