公开(公告)号：US20210091895A1

公开(公告)日：2021-03-25

申请号：US17021361

申请日：2020-09-15

Applicant: QUALCOMM Incorporated

Inventor： Cunzhen LIU ,  Alessandro RISSO ,  LI ZHANG

IPC: H04L1/18 ,  H04L1/00

Abstract: An apparatus (e.g., receive chain) for wireless communications may perform de-interleaving, de-rate matching, and hybrid automatic repeat request (HARQ) combining in a single step. The apparatus may include a data pool configured to store HARQ log likelihood ratio (LLR) data from previous transmissions. The apparatus may include a HARQ onload controller configured to load HARQ LLR data from the HARQ data pool into a HARQ buffer. The apparatus may include an LLR buffer configured to store received demodulated, interleaved, and rate matched LLR data. The apparatus may include a plurality of processing engines configured to, starting at different locations of the LLR buffer: receive new input data from the LLR buffer; combine the HARQ LLR data from the HARQ buffer with the new input data to generate de-interleaved, de-rate matched, and HARQ combined data; and write the de-interleaved, de-rate matched, and HARQ combined data into the HARQ buffer.

公开(公告)号：US20170046218A1

公开(公告)日：2017-02-16

申请号：US14823858

申请日：2015-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： MADAN KRISHNAPPA ,  CHINH TRAN ,  LI ZHANG ,  ALAN YOUNG ,  WILLIAM BAINBRIDGE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/10 ,  G06F11/1008 ,  G06F11/1048 ,  G11C11/417 ,  G11C29/42 ,  G11C29/52 ,  H03M13/11 ,  H03M13/611

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

公开(公告)号：US20130336406A1

公开(公告)日：2013-12-19

申请号：US13917291

申请日：2013-06-13

Applicant: QUALCOMM INCORPORATED

Inventor： LI ZHANG ,  YING CHEN ,  MARTA KARCZEWICZ

IPC: H04N7/34

CPC classification number: H04N19/597 ,  H04N19/105 ,  H04N19/147 ,  H04N19/176 ,  H04N19/463 ,  H04N19/593 ,  H04N19/70

Abstract: In general, techniques are described for constructing a merging candidate list for coding video data according to a merge mode and/or a skip mode. In some examples, the techniques include identifying one or more spatial merging candidates (SMCs) and an inter-view merging candidate (IVMC) for inclusion in a merging candidate list, and comparing the motion information of at least one of the SMCs to the motion information of the IVMC. In such examples, if the SMC has the same motion information as the IVMC, the techniques may further include pruning the merging candidate list to exclude the one of the merging candidates from the merging candidate list.

Abstract translation: 通常，描述了根据合并模式和/或跳过模式构建用于编码视频数据的合并候选列表的技术。 在一些示例中，所述技术包括识别一个或多个空间合并候选（SMC）和视频间合并候选（IVMC）以包括在合并候选列表中，并将至少一个SMC的运动信息与运动 IVMC的信息。 在这样的示例中，如果SMC具有与IVMC相同的运动信息，则该技术还可以包括修剪合并候选列表以从合并候选列表中排除合并候选中的一个。

公开(公告)号：US20170046219A1

公开(公告)日：2017-02-16

申请号：US14823879

申请日：2015-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： MADAN KRISHNAPPA ,  CHINH TRAN ,  LI ZHANG ,  ALAN YOUNG ,  WILLIAM BAINBRIDGE ,  Bohuslav RYCHLIK

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11

CPC classification number: G06F11/10 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/3058 ,  G06F11/3062 ,  G11B20/1816 ,  H03M13/11 ,  H03M13/611 ,  H03M13/6505 ,  Y02D10/172

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

Abstract translation: 公开了用于芯片系统（“SoC”）中的调试和/或功率管理的位翻转识别的方法和系统的各种实施例。 示例性实施例旨在通过在将数据块写入存储器组件时检查数据块的奇偶校验值来识别出现在时间附近的位翻转事件。 以这种方式，与写事务相关联发生的位翻转可以与与读取事务相关联的位翻转区分开。 当与比特翻转识别时识别的各种参数级别结合使用时，区分可能是有用的，以调试存储器组件，或者当在运行时环境中调整可能导致位翻转发生的热和功率策略时 。