公开(公告)号：US11595007B2

公开(公告)日：2023-02-28

申请号：US17081873

申请日：2020-10-27

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai ,  Manohar Seetharam

IPC: H03F1/22 ,  H03F1/26

Abstract: An active feedback low-noise amplifier includes a feedback transistor whose source couples through a feedback path to an input signal node. A bias transistor biases the source of the feedback transistor with a bias current responsive to an input signal carried on the input signal node.

公开(公告)号：US10164591B1

公开(公告)日：2018-12-25

申请号：US15684034

申请日：2017-08-23

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai ,  Tonmoy Biswas

IPC: H03F3/45 ,  H04B1/40 ,  H04W88/08 ,  H04W88/02

Abstract: Certain aspects of the present disclosure provide methods and apparatus for amplifying signals with an amplification circuit and improving a common-mode rejection ratio (CMRR) thereof. The amplification circuit generally includes a differential amplifier comprising a first pair of transistors and a second pair of transistors coupled to the first pair of transistors, where the gates of the first pair of transistors are coupled to respective differential input nodes. The amplification circuit also includes an auxiliary amplifier comprising a third pair of transistors corresponding to the first pair of transistors and a fourth pair of transistors corresponding to the second pair of transistors, where drains of the third and fourth pairs of transistors are coupled together and to gates of the second pair of transistors and where gates of the fourth pair of transistors are coupled together.

公开(公告)号：US10790805B2

公开(公告)日：2020-09-29

申请号：US15673261

申请日：2017-08-09

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai

IPC: H03H11/44 ,  H03F3/193 ,  H03F1/56 ,  H03F1/14 ,  H03H11/48 ,  H03H7/09 ,  H03H7/38 ,  H03H11/04 ,  H03H11/34 ,  H03H11/52 ,  H04B1/04

Abstract: An impedance converter circuit achieves negative capacitance and/or negative inductance for radio frequency (RF) front end impedance matching for low noise amplifier (LNA) designs. The impedance converter circuit includes a first transistor coupled to a first RF input at a source of the first transistor. The impedance converter circuit also includes a second transistor coupled to a second RF input at a source of the second transistor. The second transistor is cross-coupled to the first transistor to form a cross-coupled pair of transistors. The cross-coupled pair of transistors is configured to generate a negative capacitance or a negative inductance based on a load impedance coupled to a drain of the first transistor and a drain of the second transistor.

公开(公告)号：US10419045B1

公开(公告)日：2019-09-17

申请号：US16047563

申请日：2018-07-27

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai ,  Manohar Seetharam ,  Ehab Abdel Ghany ,  Vinod Panikkath

IPC: H04B1/04 ,  H04B1/10 ,  H04B1/18 ,  H04B1/00

Abstract: Certain aspects of the present disclosure generally relate to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element. In certain aspects, the first inductive element may be coupled in series with the third inductive element. In certain aspects, the circuit also includes a capacitive element coupled in parallel with the fourth inductive element, the capacitive element and the fourth inductive element forming a notch circuit, the notch circuit coupled in series with the second inductive element.

公开(公告)号：US10581385B2

公开(公告)日：2020-03-03

申请号：US16519877

申请日：2019-07-23

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai ,  Manohar Seetharam ,  Ehab Abdel Ghany ,  Vinod Panikkath

IPC: H03F1/26 ,  H04B1/16 ,  H03F3/193 ,  H04B1/10

Abstract: Certain aspects of the present disclosure are directed to a circuit for signal processing. The circuit generally includes a first transformer having a first inductive element magnetically coupled with a second inductive element, and a second transformer having a third inductive element magnetically coupled with a fourth inductive element, wherein the first inductive element is coupled in series with the third inductive element. In certain aspects, the circuit also includes a first switch coupled in parallel with the third inductive element, a capacitive element coupled in parallel with the fourth inductive element, wherein a notch is formed at least by the capacitive element and the fourth inductive element, the notch circuit coupled in series with the second inductive element, and a second switch coupled in parallel with the fourth inductive element.

公开(公告)号：US10541654B1

公开(公告)日：2020-01-21

申请号：US16030658

申请日：2018-07-09

Applicant: Qualcomm Incorporated

Inventor： Makar Snai ,  Ehab Abdel Ghany ,  Manohar Seetharam ,  Li-chung Chang

IPC: H03F1/22 ,  H03F1/32 ,  H03F3/193 ,  H03F3/24 ,  H04W24/02

Abstract: Amplification with post-distortion compensation is disclosed. In an example aspect, an apparatus includes a voltage rail and a cascode amplifier. The cascode amplifier includes an amplification node, a cascode node, and a common-source node. The cascode amplifier also includes at least one cascode transistor, an input transistor, and a compensation transistor. The cascode transistor is coupled between the amplification node and the cascode node. The input transistor is coupled between the cascode node and the common-source node. The compensation transistor is coupled between the voltage rail and the cascode node.

公开(公告)号：US20200014340A1

公开(公告)日：2020-01-09

申请号：US16030658

申请日：2018-07-09

Applicant: Qualcomm Incorporated

Inventor： Makar Snai ,  Ehab Abdel Ghany ,  Manohar Seetharam ,  Li-chung Chang

IPC: H03F1/32 ,  H03F3/193 ,  H03F3/24

Abstract: Amplification with post-distortion compensation is disclosed. In an example aspect, an apparatus includes a voltage rail and a cascode amplifier. The cascode amplifier includes an amplification node, a cascode node, and a common-source node. The cascode amplifier also includes at least one cascode transistor, an input transistor, and a compensation transistor. The cascode transistor is coupled between the amplification node and the cascode node. The input transistor is coupled between the cascode node and the common-source node. The compensation transistor is coupled between the voltage rail and the cascode node.