公开(公告)号：US10862461B1

公开(公告)日：2020-12-08

申请号：US16431943

申请日：2019-06-05

Applicant: QUALCOMM Incorporated

Inventor： Tonmoy Biswas ,  Sreenivasa Mallia ,  Krishnaswamy Thiagarajan ,  Ashok Swaminathan ,  Vinod Panikkath

IPC: G06F1/04 ,  H03K3/00 ,  H03K3/037 ,  H03K5/13 ,  H04B1/40 ,  H03K5/00 ,  H03K19/20

Abstract: Certain aspects of the present disclosure are directed to a circuit for switch control. The circuit generally includes a plurality of flip-flops, each of the plurality of flip-flops having an input coupled to a respective one of a plurality of enable signals, a NOR gate having inputs coupled to outputs of the plurality of flip-flops; a plurality of AND gates, each having an input coupled to a respective one of the plurality of enable signals and having another input coupled to an output of the NOR gate, and a delay element coupled between the output of the NOR gate and reset inputs of the plurality of flip-flops.

公开(公告)号：US10164591B1

公开(公告)日：2018-12-25

申请号：US15684034

申请日：2017-08-23

Applicant: QUALCOMM Incorporated

Inventor： Makar Snai ,  Tonmoy Biswas

IPC: H03F3/45 ,  H04B1/40 ,  H04W88/08 ,  H04W88/02

Abstract: Certain aspects of the present disclosure provide methods and apparatus for amplifying signals with an amplification circuit and improving a common-mode rejection ratio (CMRR) thereof. The amplification circuit generally includes a differential amplifier comprising a first pair of transistors and a second pair of transistors coupled to the first pair of transistors, where the gates of the first pair of transistors are coupled to respective differential input nodes. The amplification circuit also includes an auxiliary amplifier comprising a third pair of transistors corresponding to the first pair of transistors and a fourth pair of transistors corresponding to the second pair of transistors, where drains of the third and fourth pairs of transistors are coupled together and to gates of the second pair of transistors and where gates of the fourth pair of transistors are coupled together.

公开(公告)号：US10454509B2

公开(公告)日：2019-10-22

申请号：US15962865

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Bhushan Shanti Asuri ,  Krishnaswamy Thiagarajan ,  Ashok Swaminathan ,  Shahin Mehdizad Taleie ,  Yen-Wei Chang ,  Vinod Panikkath ,  Sameer Vasantlal Vora ,  Ayush Mittal ,  Tonmoy Biswas ,  Sy-Chyuan Hwu ,  Zhilong Tang ,  Ibrahim Chamas ,  Ping Wing Lai ,  Behnam Sedighi ,  Dongwon Seo ,  Nitz Saputra

IPC: H04B1/04 ,  H04L27/20 ,  H04B1/00

Abstract: A communication circuit may include a first pair of digital-to-analog converters (DACs) coupled to an input of a first mixer and configured to generate first baseband signals. The communication circuit may further include a second pair of DACs coupled to an input of a second mixer and configured to generate second baseband signals. The second baseband signals may be shifted in phase relative to the first baseband signals.