-
1.
公开(公告)号:US20180226387A1
公开(公告)日:2018-08-09
申请号:US15941611
申请日:2018-03-30
发明人: Chan Yoo , Todd O. Bolken
IPC分类号: H01L25/10 , H01L23/00 , H01L21/56 , H01L23/495 , H01L21/82 , H01L25/065 , H01L23/31
CPC分类号: H01L25/105 , H01L21/56 , H01L21/561 , H01L21/565 , H01L21/566 , H01L21/82 , H01L23/3128 , H01L23/3142 , H01L23/495 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/97 , H01L25/0657 , H01L2224/02377 , H01L2224/0401 , H01L2224/04042 , H01L2224/05568 , H01L2224/05573 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/06177 , H01L2224/1012 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/12105 , H01L2224/1301 , H01L2224/13014 , H01L2224/13017 , H01L2224/13024 , H01L2224/13144 , H01L2224/13147 , H01L2224/14051 , H01L2224/16055 , H01L2224/16057 , H01L2224/16058 , H01L2224/16145 , H01L2224/16238 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2224/49175 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2224/85 , H01L2224/92163 , H01L2224/92247 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/0652 , H01L2225/06565 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/12042 , H01L2924/15184 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00012 , H01L2924/00 , H01L2924/0665 , H01L2224/83
摘要: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a spacer material on an encapsulant such that the encapsulant separates the spacer material from an active surface of a semiconductor device and at least one interconnect projecting away from the active surface. The method further includes molding the encapsulant such that at least a portion of the interconnect extends through the encapsulant and into the spacer material. The interconnect can include a contact surface that is substantially co-planar with the active surface of the semiconductor device for providing an electrical connection with the semiconductor device.
-
公开(公告)号:US10008477B2
公开(公告)日:2018-06-26
申请号:US15286086
申请日:2016-10-05
申请人: Invensas Corporation
发明人: Belgacem Haba , Richard Dewitt Crisp , Wael Zohni
IPC分类号: H01L21/48 , H01L23/29 , H01L23/31 , H01L23/49 , H01L21/56 , H01L25/065 , H01L23/00 , H01L25/00
CPC分类号: H01L25/0657 , H01L21/4846 , H01L21/565 , H01L23/293 , H01L23/3128 , H01L23/3171 , H01L23/49 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/742 , H01L24/745 , H01L24/81 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05571 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1134 , H01L2224/1184 , H01L2224/1191 , H01L2224/13005 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/13017 , H01L2224/13022 , H01L2224/13076 , H01L2224/131 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1357 , H01L2224/13624 , H01L2224/13655 , H01L2224/1369 , H01L2224/14051 , H01L2224/16105 , H01L2224/16108 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/32145 , H01L2224/73103 , H01L2224/73203 , H01L2224/73253 , H01L2224/73267 , H01L2224/742 , H01L2224/81191 , H01L2224/81193 , H01L2224/81815 , H01L2224/9202 , H01L2224/92142 , H01L2224/92143 , H01L2224/97 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06555 , H01L2225/06568 , H01L2225/06582 , H01L2225/06589 , H01L2924/12042 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00012 , H01L2924/207 , H01L2224/83 , H01L2224/11 , H01L2224/81 , H01L2924/00
摘要: A microelectronic structure includes a semiconductor having conductive elements at a first surface. Wire bonds have bases joined to the conductive elements and free ends remote from the bases, the free ends being remote from the substrate and the bases and including end surfaces. The wire bonds define edge surfaces between the bases and end surfaces thereof. A compliant material layer extends along the edge surfaces within first portions of the wire bonds at least adjacent the bases thereof and fills spaces between the first portions of the wire bonds such that the first portions of the wire bonds are separated from one another by the compliant material layer. Second portions of the wire bonds are defined by the end surfaces and portions of the edge surfaces adjacent the end surfaces that are extend from a third surface of the compliant later.
-
公开(公告)号:US09960105B2
公开(公告)日:2018-05-01
申请号:US13631939
申请日:2012-09-29
申请人: INTEL CORPORATION
发明人: Hongin Jiang , Arun Kumar C. Nallani , Wei Tan
IPC分类号: H01L23/498 , H01L23/48 , H01L21/48
CPC分类号: H01L23/49811 , H01L21/4853 , H01L23/48 , H01L23/49816 , H01L2224/1403 , H01L2224/14051 , H01L2924/0002 , H01L2924/15311 , H01L2924/3511 , H01L2924/00
摘要: An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material comprising a solder positioned on the bonding pads and extending a distance outward therefrom. A first of the bonding pads in a first location on the substrate surface includes the solder extending a first distance outward therefrom. A second of the bonding pads in a second location on the substrate surface includes the solder extending a second distance outward therefrom. The first distance is different than the second distance. Other embodiments are described and claimed.
-
公开(公告)号:US20180076162A1
公开(公告)日:2018-03-15
申请号:US15804478
申请日:2017-11-06
IPC分类号: H01L23/00 , H01L25/00 , B23K3/06 , H01L23/522 , H01L23/498 , H01L23/34 , H01L21/768 , H01L21/48 , H01L25/065 , H01L23/488 , H01L23/48
CPC分类号: H01L24/13 , B23K3/0623 , H01L21/4867 , H01L21/76802 , H01L21/76877 , H01L23/34 , H01L23/345 , H01L23/481 , H01L23/488 , H01L23/49816 , H01L23/49894 , H01L23/5226 , H01L24/08 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/742 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05027 , H01L2224/11013 , H01L2224/1131 , H01L2224/11312 , H01L2224/11416 , H01L2224/1148 , H01L2224/11618 , H01L2224/13013 , H01L2224/13014 , H01L2224/13015 , H01L2224/13109 , H01L2224/13111 , H01L2224/14051 , H01L2224/16111 , H01L2224/16145 , H01L2224/16227 , H01L2224/16238 , H01L2224/17519 , H01L2224/27 , H01L2224/27416 , H01L2224/27515 , H01L2224/27618 , H01L2224/29011 , H01L2224/29012 , H01L2224/29076 , H01L2224/29109 , H01L2224/29111 , H01L2224/2919 , H01L2224/73104 , H01L2224/73204 , H01L2224/81 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81204 , H01L2224/81801 , H01L2224/81815 , H01L2224/83 , H01L2224/83203 , H01L2224/83204 , H01L2224/9211 , H01L2224/94 , H01L2225/06513 , H01L2225/06568 , H01L2924/00 , H01L2924/014 , H01L2924/06 , H01L2924/12042 , H01L2924/3512 , H01L2924/37001 , H01L2924/3841 , H01L2224/11 , H01L2924/00014 , H01L2924/0103 , H01L2924/01083 , H01L2924/01049 , H01L2924/01051 , H01L2924/01028 , H01L2924/01027 , H01L2924/01032 , H01L2924/01026 , H01L2924/01047 , H01L2924/01029 , H01L2924/00013 , H01L2924/00012
摘要: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.
-
公开(公告)号:US20180047692A1
公开(公告)日:2018-02-15
申请号:US15233271
申请日:2016-08-10
发明人: Glenn Rinne , Daniel Richter
IPC分类号: H01L23/00
CPC分类号: H01L24/14 , H01L23/49816 , H01L23/49838 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/81 , H01L2224/06051 , H01L2224/06177 , H01L2224/11849 , H01L2224/119 , H01L2224/13012 , H01L2224/13014 , H01L2224/13015 , H01L2224/13016 , H01L2224/13017 , H01L2224/131 , H01L2224/14051 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/14141 , H01L2224/14151 , H01L2224/14153 , H01L2224/14154 , H01L2224/14177 , H01L2224/81815 , H01L2924/10156 , H01L2924/15311 , H01L21/78 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要: Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.
-
公开(公告)号:US20180033757A1
公开(公告)日:2018-02-01
申请号:US15720127
申请日:2017-09-29
发明人: Akira YAJIMA
IPC分类号: H01L23/00
CPC分类号: H01L24/14 , H01L23/3192 , H01L23/525 , H01L23/53214 , H01L23/53228 , H01L23/5329 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02331 , H01L2224/02377 , H01L2224/0239 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03614 , H01L2224/03914 , H01L2224/0401 , H01L2224/05024 , H01L2224/05073 , H01L2224/0508 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05187 , H01L2224/05664 , H01L2224/10126 , H01L2224/10145 , H01L2224/11334 , H01L2224/11849 , H01L2224/119 , H01L2224/11901 , H01L2224/13017 , H01L2224/13024 , H01L2224/131 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14051 , H01L2224/14131 , H01L2224/14133 , H01L2224/14135 , H01L2224/14177 , H01L2224/14179 , H01L2224/14517 , H01L2224/16058 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/16238 , H01L2224/17051 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/81139 , H01L2224/81191 , H01L2224/81192 , H01L2224/81193 , H01L2224/814 , H01L2224/81411 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/0132 , H01L2924/0133 , H01L2924/07025 , H01L2924/15311 , H01L2924/351 , H01L2924/381 , H01L2924/00012 , H01L2924/014 , H01L2924/0665 , H01L2924/01022 , H01L2924/04941 , H01L2924/01029 , H01L2924/01028 , H01L2924/01074 , H01L2924/01024 , H01L2924/01073 , H01L2924/0496 , H01L2924/01046 , H01L2924/01044 , H01L2924/01078 , H01L2924/01047 , H01L2924/00014 , H01L2924/00
摘要: In the semiconductor device, a bump electrode which connects a semiconductor chip and a wiring board is made up of a first part surrounded by an insulating film and a second part exposed from the insulating film. Since it is possible to reduce a width of the bump electrode while increasing a height of the bump electrode, a distance between the neighboring bump electrodes can be increased, and a filling property of a sealing material can be improved.
-
公开(公告)号:US20180026008A1
公开(公告)日:2018-01-25
申请号:US15722983
申请日:2017-10-02
发明人: Shin-Puu Jeng , Shang-Yun Hou , Kim Hong Chen , Wensen Hung , Szu-Po Huang
IPC分类号: H01L25/065 , H01L21/48 , H01L23/00 , H01L23/538 , H01L23/498 , H01L23/31 , H01L23/13 , H01L21/683 , H01L21/56 , H01L25/18 , H01L25/00 , H01L23/367 , H01L23/42
CPC分类号: H01L25/0652 , H01L21/4853 , H01L21/4857 , H01L21/561 , H01L21/563 , H01L21/6835 , H01L23/13 , H01L23/3128 , H01L23/3135 , H01L23/367 , H01L23/3677 , H01L23/42 , H01L23/49822 , H01L23/49827 , H01L23/49833 , H01L23/49838 , H01L23/5389 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/97 , H01L25/18 , H01L25/50 , H01L2221/68327 , H01L2221/68331 , H01L2224/0401 , H01L2224/11 , H01L2224/11002 , H01L2224/11003 , H01L2224/1111 , H01L2224/11334 , H01L2224/1183 , H01L2224/11848 , H01L2224/131 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/1403 , H01L2224/14051 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/1703 , H01L2224/2919 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/81 , H01L2224/81005 , H01L2224/81191 , H01L2224/81192 , H01L2224/81805 , H01L2224/83 , H01L2224/92125 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/06548 , H01L2225/06568 , H01L2225/06572 , H01L2225/06589 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/01322 , H01L2924/04941 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/15153 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/15321 , H01L2924/157 , H01L2924/181 , H01L2924/18161 , H01L2924/2075 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/00012 , H01L2924/00 , H01L2924/014
摘要: Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.
-
公开(公告)号:US09847238B2
公开(公告)日:2017-12-19
申请号:US15443371
申请日:2017-02-27
申请人: Invensas Corporation
发明人: Xuan Li , Rajesh Katkar , Long Huynh , Laura Wills Mirkarimi , Bongsub Lee , Gabriel Z. Guevara , Tu Tam Vu , Kyong-Mo Bang , Akash Agrawal
IPC分类号: H01L21/56 , H01L21/683 , H01L21/768 , H01L25/00 , H01L21/02 , H01L23/00 , H01L21/304 , H01L23/29 , H01L25/065
CPC分类号: H01L21/568 , H01L21/02118 , H01L21/304 , H01L21/4846 , H01L21/561 , H01L21/565 , H01L21/6835 , H01L21/76838 , H01L21/76892 , H01L23/293 , H01L23/3135 , H01L23/4985 , H01L23/5384 , H01L24/09 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/19 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13006 , H01L2224/131 , H01L2224/1403 , H01L2224/14051 , H01L2224/16111 , H01L2224/16237 , H01L2224/27436 , H01L2224/29011 , H01L2224/2919 , H01L2224/73203 , H01L2224/73267 , H01L2224/81005 , H01L2224/8114 , H01L2224/81191 , H01L2224/8185 , H01L2224/81903 , H01L2224/81904 , H01L2224/8192 , H01L2224/83192 , H01L2224/83856 , H01L2224/92244 , H01L2224/97 , H01L2924/15311 , H01L2224/81 , H01L2924/0665 , H01L2924/00014 , H01L2924/014
摘要: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.
-
公开(公告)号:US09831201B2
公开(公告)日:2017-11-28
申请号:US14644473
申请日:2015-03-11
IPC分类号: H01L23/00
CPC分类号: H01L24/11 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L2224/03426 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05073 , H01L2224/05082 , H01L2224/05124 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05172 , H01L2224/05184 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05671 , H01L2224/05672 , H01L2224/05684 , H01L2224/1132 , H01L2224/1147 , H01L2224/11474 , H01L2224/11505 , H01L2224/11849 , H01L2224/119 , H01L2224/11902 , H01L2224/13006 , H01L2224/13007 , H01L2224/13012 , H01L2224/13013 , H01L2224/13014 , H01L2224/132 , H01L2224/13294 , H01L2224/133 , H01L2224/13301 , H01L2224/13305 , H01L2224/13309 , H01L2224/13311 , H01L2224/13313 , H01L2224/13316 , H01L2224/13318 , H01L2224/1332 , H01L2224/13324 , H01L2224/13339 , H01L2224/13344 , H01L2224/13347 , H01L2224/13355 , H01L2224/13364 , H01L2224/1403 , H01L2224/14051 , H01L2924/00015 , H01L2924/01013 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01031 , H01L2924/01046 , H01L2924/01047 , H01L2924/01048 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/381 , H01L2224/11462 , H01L2924/00014 , H01L2924/00012 , H01L2224/034 , H01L2224/036
摘要: The subject matter contained herein discloses methods for forming a vertical metallic pillar overlying an under bump metal pad further overlying a semiconductor substrate, and applying a discrete solder cap on a top surface of the pillar, wherein the metallic pillar is defined by at least one photoresist layer. The method includes heating a multi-element metallic paste containing a variable amount of metallic powder, a melting point depressant and a flux such that the metal powder sinters to form the metallic pillar and simultaneously adheres the metallic pillar to the underbump metal pad.
-
公开(公告)号:US20170309588A1
公开(公告)日:2017-10-26
申请号:US15646721
申请日:2017-07-11
发明人: Sheng-Yu Wu , Tin-Hao Kuo , Chita Chuang , Chen-Shien Chen
IPC分类号: H01L23/00 , H01L23/522 , H01L23/532 , H01L21/56 , H01L23/58 , H01L23/31 , H01L21/60
CPC分类号: H01L24/17 , H01L21/563 , H01L23/3171 , H01L23/522 , H01L23/53238 , H01L23/562 , H01L23/585 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2021/60255 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05027 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05541 , H01L2224/05569 , H01L2224/05572 , H01L2224/05582 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05671 , H01L2224/05684 , H01L2224/06102 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/13022 , H01L2224/13024 , H01L2224/13082 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14152 , H01L2224/14179 , H01L2224/16237 , H01L2224/16238 , H01L2224/17104 , H01L2224/17517 , H01L2224/73204 , H01L2224/81007 , H01L2224/81101 , H01L2224/81191 , H01L2224/81815 , H01L2224/83104 , H01L2924/01029 , H01L2924/01047 , H01L2924/04941 , H01L2924/04953 , H01L2924/15787 , H01L2924/15788 , H01L2924/35 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/206 , H01L2924/00
摘要: A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer.
-
-
-
-
-
-
-
-
-