公开(公告)号：US20250096111A1

公开(公告)日：2025-03-20

申请号：US18467163

申请日：2023-09-14

Applicant: QUALCOMM Incorporated

Inventor： Michelle Yejin KIM ,  Hong Bok WE ,  Joan Rey Villarba BUOT ,  Kuiwon KANG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

Abstract: A package comprising an integrated device; and a substrate coupled to the integrated device through at least a plurality of solder interconnects. The substrate comprises a core layer comprising a cavity; a region comprising a passive component block located at least partially in the cavity of the core layer, wherein the passive component block comprises a first passive device and a second passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

公开(公告)号：US20240321763A1

公开(公告)日：2024-09-26

申请号：US18189991

申请日：2023-03-24

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes (i) a first cored substrate portion comprising a first core layer comprising a first cavity, a first integrated device located in the first cavity of the first core layer, and a first dielectric layer encapsulating the first integrated device; and (ii) a second cored substrate portion comprising a second core layer comprising a second cavity, a second integrated device located in the second cavity of the second core layer and a second dielectric layer encapsulating the second integrated device.

公开(公告)号：US20220102298A1

公开(公告)日：2022-03-31

申请号：US17038124

申请日：2020-09-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Michelle Yejin KIM ,  Marcus HSU

IPC: H01L23/00

Abstract: Aspects disclosed herein include a device including a bump pad structure and methods for fabricating the same. The device includes a bump pad. The device also includes a first trace adjacent the bump pad, where a first trace top surface is recessed a first recess distance from a bump pad top surface. The device also includes a second trace adjacent the first trace, covered at least in part by a solder resist. The device also includes a substrate, where the bump pad, the first trace, and the second trace are each formed on a portion of the substrate.

公开(公告)号：US20250070034A1

公开(公告)日：2025-02-27

申请号：US18455368

申请日：2023-08-24

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device includes a substrate including first conductors connecting contacts on a first side of the substrate to contacts on a second side of the substrate. The first conductors include metal lines arranged in metal layers separated from one another by dielectric layers and conductive vias interconnecting the metal lines. The substrate also includes second conductors connecting contacts on the first side of the substrate to contacts on the first side of the substrate to define conductive paths between a first die and a second die. The second conductors include metal lines arranged in metal layers that are separated from one another by dielectric layers and conductive vias interconnecting the metal lines of the second conductors. At least one metal layer of the second conductors is devoid of the metal lines of the first conductors.

公开(公告)号：US20230282585A1

公开(公告)日：2023-09-07

申请号：US17684327

申请日：2022-03-01

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386

Abstract: A package that includes a substrate, a first integrated device coupled to the substrate, and a second integrated device coupled to the substrate. The substrate includes at least one dielectric layer, and a plurality of interconnects comprising a plurality of escape interconnects. The plurality of escape interconnects includes a first embedded escape interconnect, a second embedded escape interconnect, and a third escape interconnect located between the first embedded escape interconnect and the second embedded escape interconnect.

公开(公告)号：US20250079348A1

公开(公告)日：2025-03-06

申请号：US18458650

申请日：2023-08-30

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Hong Bok WE ,  Michelle Yejin KIM

IPC: H01L23/64 ,  H01L21/768 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/498

Abstract: A substrate comprising: a core layer comprising a cavity; an embedded passive device located at least partially in the cavity of the core layer, wherein the embedded passive device comprises a plurality of pad interconnects; a polyimide layer coupled to a surface of the embedded passive device; at least one dielectric layer coupled to the core layer; and a plurality of interconnects located at least partially in the at least one dielectric layer.

公开(公告)号：US20240371775A1

公开(公告)日：2024-11-07

申请号：US18310388

申请日：2023-05-01

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Kuiwon KANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: In an aspect, a substrate includes a core that includes a core dielectric and a first conductive pattern on a first surface of the core dielectric, and a first metallization structure over the first surface of the core dielectric. The first metallization structure includes a first dielectric, and the first dielectric has a first opening formed therein. The substrate further includes a first electronic component disposed in the first opening of the first dielectric, and a first adhesive layer coupling the first electronic component with the core.

公开(公告)号：US20240079307A1

公开(公告)日：2024-03-07

申请号：US17939769

申请日：2022-09-07

Applicant: QUALCOMM Incorporated

Inventor： Wei WANG ,  Kuiwon KANG ,  Michelle Yejin KIM ,  Ahmer SYED

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/35121

Abstract: A package comprising an integrated device and a substrate coupled to the integrated device. The substrate comprises at least one dielectric layer and a plurality of interconnects. The plurality of interconnects include a plurality of post interconnects. The plurality of post interconnects include a post interconnect comprising a profile cross section that includes a trapezoid shape.

公开(公告)号：US20250140700A1

公开(公告)日：2025-05-01

申请号：US18494115

申请日：2023-10-25

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Hong Bok WE ,  Michelle Yejin KIM ,  Aniket PATIL ,  Yu-Ting HUANG

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/10

Abstract: In an aspect, a substrate for an integrated circuit (IC) package includes a first dielectric layer, a first metallization layer on a first surface of the first dielectric layer and including a first pad structure and a first trace structure, a second metallization layer on a second surface of the first dielectric layer and including a second pad structure and a second trace structure, a second dielectric layer on the second surface of the first dielectric layer, and a third metallization layer on a second surface of the second dielectric layer and having a third pad structure. The substrate further includes a conductive stud coupled to the second pad structure and a second via structure embedded in the second dielectric layer. The second via structure has a first end coupled to the conductive stud and a second end coupled to the third pad structure.

公开(公告)号：US20250070086A1

公开(公告)日：2025-02-27

申请号：US18455928

申请日：2023-08-25

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Joan Rey Villarba BUOT ,  Michelle Yejin KIM ,  Manuel ALDRETE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A device includes a bottom substrate including first conductors, a top substrate including second conductors, and a first die disposed between the bottom substrate and the top substrate. The first die includes circuitry and first contacts electrically connected to the circuitry and to the first conductors. The device also includes a redistribution die disposed between the bottom substrate and the top substrate adjacent to the first die. The redistribution die includes second contacts electrically connected to the first contacts through the first conductors and third contacts electrically connected to the second conductors. The redistribution die also includes redistribution traces electrically connected to the second contacts and to the third contacts. The top substrate includes fourth contacts electrically connected through the second conductors to the third contacts to define one or more signal paths between the fourth contacts and the first die.