公开(公告)号：US11029748B2

公开(公告)日：2021-06-08

申请号：US15070381

申请日：2016-03-15

申请人： QUALCOMM Incorporated

发明人： Neven Klacar ,  Muralidhar Krishnamoorthy ,  Hariharan Sukumar

IPC分类号： G06F1/3234 ,  G06F1/3206 ,  G06F13/42 ,  G06F1/3237 ,  G06F1/3215 ,  G06F13/10 ,  G06F13/28 ,  G06F13/40

摘要： Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.

公开(公告)号：US20170269675A1

公开(公告)日：2017-09-21

申请号：US15070381

申请日：2016-03-15

申请人： QUALCOMM Incorporated

发明人： Neven Klacar ,  Muralidhar Krishnamoorthy ,  Hariharan Sukumar

IPC分类号： G06F1/32 ,  G06F13/42 ,  G06F13/40 ,  G06F13/10 ,  G06F13/28

CPC分类号： G06F1/3278 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/3253 ,  G06F13/102 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4291 ,  G06F13/4295 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, methods, and apparatus for adaptively modifying latency times governing entry of a PCIe interface into low power states are described. A method performed by a controller of a PCIe interface includes determining that a burst of data is being transmitted on a PCIe link, configuring a timer to signal when an entry latency period has elapsed after determining that a PCIe link has entered an idle state, causing one or more circuits of the PCIe interface to enter a low-power state when the timer signals that the entry latency period has elapsed before the PCIe link becomes active, and increasing the entry latency period when a number of entries of the PCIe interface to the low-power state that occurs during transmission of the burst of data exceeds a threshold maximum number.