公开(公告)号：US20220208232A1

公开(公告)日：2022-06-30

申请号：US17136616

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/06 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20250132255A1

公开(公告)日：2025-04-24

申请号：US18492613

申请日：2023-10-23

Applicant: QUALCOMM Incorporated

Inventor： Channappa DESAI ,  Sunil SHARMA ,  Rahul BIRADAR ,  Ramakoti NIMMAKAYALA ,  Prasanth KONDALAMPATTI SEKAR ,  Anne SRIKANTH

IPC: H01L23/528 ,  H01L23/522

Abstract: Aspects of the present disclosure provide a filler cell that may be placed next to the active cell to reduce a current-resistor (IR) drop for the active cell. The filler cell includes an active dummy device coupled to a source of a transistor in the active cell and a rail (e.g., a ground rail or a voltage supply rail). The filler cell provides the active cell with at least one additional current path between the source of the transistor and the rail through the active dummy device, which reduces the IR drop between the source of the transistor and the rail.

公开(公告)号：US20230178118A1

公开(公告)日：2023-06-08

申请号：US18163146

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.