公开(公告)号：US20230178118A1

公开(公告)日：2023-06-08

申请号：US18163146

申请日：2023-02-01

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/06 ,  G11C7/10 ,  G11C8/08 ,  G11C8/10

CPC classification number: G11C5/025 ,  G11C7/06 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20220208232A1

公开(公告)日：2022-06-30

申请号：US17136616

申请日：2020-12-29

Applicant: QUALCOMM Incorporated

Inventor： David LI ,  Rahul BIRADAR ,  Biju MANAKKAM VEETIL ,  Po-Hung CHEN ,  Ayan PAUL ,  Sung SON ,  Shivendra KUSHWAHA ,  Ravindra Reddy CHEKKERA ,  Derek YANG

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/06 ,  G11C8/08 ,  G11C8/10

Abstract: A semiconductor device includes: a memory circuit having a plurality of quadrants arranged at corners of the memory circuit and surrounding a bank control component; wherein a first quadrant of the plurality of quadrants includes a first bit cell core and a first set of input output circuits configured to access the first bit cell core, the first quadrant defined by a rectangular boundary that encloses portions of two perpendicular edges of the memory circuit; wherein a second quadrant of the plurality of quadrants includes a second bit cell core and a second set of input output circuits configured to access the second bit cell core, the second quadrant being adjacent the first quadrant, wherein a border between the first quadrant and the second quadrant defines a first axis about which the first quadrant and the second quadrant are symmetrical.

公开(公告)号：US20240257868A1

公开(公告)日：2024-08-01

申请号：US18104167

申请日：2023-01-31

Applicant: QUALCOMM Incorporated

Inventor： Chulmin JUNG ,  David LI ,  Po-Hung CHEN ,  Ayan PAUL ,  Derek YANG ,  Chun-Yen LIN

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory is provided with a pseudo-differential sense amplifier for single-endedly sensing a first read bit line from a first bank of bitcells. The sense amplifier compares a voltage of the first read bit line to a voltage of a pre-charged second read bit line from a second bank of bitcells to make a bit decision for a read operation through the first read bit line to the first bank of bitcells.

公开(公告)号：US20180166129A1

公开(公告)日：2018-06-14

申请号：US15379285

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： Darshit MEHTA ,  Chulmin JUNG ,  Po-Hung CHEN

IPC: G11C11/419 ,  G06F3/06

CPC classification number: G11C11/419 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1096 ,  G11C2207/002

Abstract: The apparatus provided may be a memory circuit. The memory circuit includes a memory cell. The memory cell has a bitline. The memory circuit also includes a write driver. The write driver is configured to drive the bitline to write a bit to the memory cell during a write operation. The write driver is also configured to float the bitline to mask the bit during a read operation. The write driver may use NMOS pullup transistors.