公开(公告)号：US20160164698A1

公开(公告)日：2016-06-09

申请号：US14559429

申请日：2014-12-03

Applicant: QUALCOMM Incorporated

Inventor： Richard Gerard HOFMANN ,  Ryan WELLS ,  Vijay NAGARAJ ,  Prudhvi Nadh NOONEY

IPC: H04L12/40 ,  H04L12/26

CPC classification number: H04L12/4013 ,  H04L12/423 ,  H04L43/16

Abstract: Systems and methods for relate to bus ring performance monitoring and control. A bus ring includes an agent and a switch unit to connect the agent to the bus ring. The switch unit includes a transmit queue to store data from the bus ring to be transmitted to the agent and a receive queue to store data from the agent to be transmitted to the bus ring. A first counter is implemented to track a number of pending transactions in the transmit queue and a second counter is implemented to track a number of times the receive queue is full and unable to accept additional data. Frequency of the bus ring is increased or decreased based on comparison of values of the first counter and the second counter with corresponding predefined high and low threshold values.

Abstract translation: 与总线环性能监测和控制相关的系统和方法。 总线环包括代理和用于将代理连接到总线环的交换单元。 交换单元包括发送队列，用于存储来自总线环的数据以发送到代理，以及接收队列，用于存储来自代理的数据以发送到总线环。 实现第一计数器以跟踪发送队列中的多个待处理事务，并且实现第二计数器以跟踪接收队列已满并且不能接受附加数据的次数。 基于第一计数器和第二计数器的值与相应的预定义的高和低阈值的比较来增加或减少总线环的频率。

公开(公告)号：US20180074568A1

公开(公告)日：2018-03-15

申请号：US15814361

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Ryan WELLS ,  Norman GARGASH ,  Rodney Wayne SMITH

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.