APPARATUS AND METHOD FOR DYNAMIC POWER REDUCTION IN A UNIFIED SCHEDULER

    公开(公告)号:US20170285727A1

    公开(公告)日:2017-10-05

    申请号:US15086049

    申请日:2016-03-30

    CPC classification number: G06F1/3287 G06F9/3836 G06F9/3869

    Abstract: A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.

    HIERARCHICAL REGISTER FILE SYSTEM
    5.
    发明申请
    HIERARCHICAL REGISTER FILE SYSTEM 审中-公开
    分层寄存器文件系统

    公开(公告)号:US20170060593A1

    公开(公告)日:2017-03-02

    申请号:US14843921

    申请日:2015-09-02

    CPC classification number: G06F9/30105 G06F9/30138 G06F9/384 G06F9/3867

    Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.

    Abstract translation: 系统和方法涉及包括1级物理寄存器文件(L1 PRF)和后置物理寄存器文件(PRF)的分级寄存器文件系统。 识别在处理器的指令流水线中执行的指令的生成的子集,其具有用于一个或多个未来指令的高似然性。 生产的子集存储在L1 PRF中,而所有生产都存储在后备PRF中。

    POWER EFFICIENT FETCH ADAPTATION
    8.
    发明申请
    POWER EFFICIENT FETCH ADAPTATION 审中-公开
    功率有效的FET适配

    公开(公告)号:US20170046159A1

    公开(公告)日:2017-02-16

    申请号:US14827262

    申请日:2015-08-14

    Abstract: Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.

    Abstract translation: 系统和方法涉及诸如超标量处理器的处理器的指令提取单元。 指令提取单元包括获取带宽预测器(FBWP),其被配置为预测将在处理器的流水线级中的取指令组中提取的指令数量。 对应于取出组的FBWP的第一条目对应于基于取出组中预测的分支指令的出现和位置以及与所提取的预测数相关联的置信水平的待提取的指令数量的预测 预测领域。 如果置信水平大于预定阈值,则指令提取单元被配置为仅获取预测数量的指令,而不是在流水线级中可以获取的最大条目数。 以这种方式,避免了浪费的指令提取。

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