公开(公告)号：US20170285727A1

公开(公告)日：2017-10-05

申请号：US15086049

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram KULKARNI ,  Rami Mohammad A. AL SHEIKH ,  Raguram DAMODARAN

IPC: G06F1/32 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F9/3836 ,  G06F9/3869

Abstract: A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.

公开(公告)号：US20170249149A1

公开(公告)日：2017-08-31

申请号：US15057116

申请日：2016-02-29

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Rami Mohammad AL SHEIKH ,  Raguram DAMODARAN ,  Michael Scott MCILVAINE ,  Jeffrey Todd BRIDGES

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30083 ,  G06F9/30021 ,  G06F9/30058 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3867

Abstract: Systems and methods for operating a processor include determining confidence levels, such as high, low, and medium confidence levels, associated with in-flight branch instructions in an instruction pipeline of the processor, based on counters used for predicting directions of the in-flight branch instructions. Numbers of in-flight branch instructions associated with each of confidence levels are determined. A weighted sum of the numbers weighted with weights corresponding to the confidence levels is calculated and the weighted sum is compared with a threshold. A throttling signal may be asserted to indicate that instructions are to be throttled in a pipeline stage of the instruction pipeline based on the comparison.

公开(公告)号：US20170090508A1

公开(公告)日：2017-03-30

申请号：US14865092

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Thomas Philip SPEIER ,  Rodney Wayne SMITH ,  Keith Alan BOWMAN ,  David Joseph Winston HANSQUINE

IPC: G06F1/08 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F1/08 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3861 ,  G06F12/0804 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/12 ,  G06F2212/1024 ,  G06F2212/60 ,  Y02D10/126 ,  Y02D10/152

Abstract: The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.

公开(公告)号：US20180074568A1

公开(公告)日：2018-03-15

申请号：US15814361

申请日：2017-11-15

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Anil KRISHNA ,  Raguram DAMODARAN ,  Jeffrey Todd BRIDGES ,  Ryan WELLS ,  Norman GARGASH ,  Rodney Wayne SMITH

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

公开(公告)号：US20170060593A1

公开(公告)日：2017-03-02

申请号：US14843921

申请日：2015-09-02

Applicant: QUALCOMM Incorporated

Inventor： Anil KRISHNA ,  Rodney Wayne SMITH ,  Sandeep Suresh NAVADA ,  Shivam PRIYADARSHI ,  Niket Kumar CHOUDHARY ,  Raguram DAMODARAN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30105 ,  G06F9/30138 ,  G06F9/384 ,  G06F9/3867

Abstract: Systems and methods relate to a hierarchical register file system including a level 1 physical register file (L1 PRF) and a backing physical register file (PRF). A subset of productions of instructions executed in an instruction pipeline of a processor which have a high likelihood of use for one or more future instructions are identified. The subset of productions are stored in the L1 PRF, while all productions are stored in the backing PRF.

Abstract translation: 系统和方法涉及包括1级物理寄存器文件（L1 PRF）和后置物理寄存器文件（PRF）的分级寄存器文件系统。 识别在处理器的指令流水线中执行的指令的生成的子集，其具有用于一个或多个未来指令的高似然性。 生产的子集存储在L1 PRF中，而所有生产都存储在后备PRF中。

公开(公告)号：US20170286120A1

公开(公告)日：2017-10-05

申请号：US15086052

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram KULKARNI ,  Rami Mohammad A. AL SHEIKH ,  Raguram DAMODARAN

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3005 ,  G06F9/3836 ,  G06F9/3838

Abstract: A scheduler with a picker block capable of dispatching multiple instructions per cycle is disclosed. The picker block may comprise an inter-group picker and an intra-group picker. The inter-group picker may be configured to pick multiple ready groups when there are two or more ready groups among a plurality of groups of instructions, and pick a single ready group when the single ready group is the only ready group among the plurality of groups. The intra-group picker may be configured to pick one ready instruction from each of the multiple ready groups when the inter-group picker picks the multiple ready groups, and to pick multiple ready instructions from the single ready group when the inter-group picker picks the single ready group.

公开(公告)号：US20170091117A1

公开(公告)日：2017-03-30

申请号：US14865049

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Harold Wade CAIN, III ,  Derek Robert HOWER ,  Raguram DAMODARAN ,  Thomas Andrew SARTORIUS

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0842 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/12 ,  G06F2212/1044 ,  G06F2212/621 ,  Y02D10/13

Abstract: A cache fill line is received, including an index, a thread identifier, and cache fill line data. The cache is probed, using the index and a different thread identifier, for a potential duplicate cache line. The potential duplicate cache line includes cache line data and the different thread identifier. Upon the cache fill line data matching the cache line data, duplication is identified. The potential duplicate cache line is set as a shared resident cache line, and the thread share permission tag is set to a permission state.

公开(公告)号：US20170046159A1

公开(公告)日：2017-02-16

申请号：US14827262

申请日：2015-08-14

Applicant: QUALCOMM Incorporated

Inventor： Shivam PRIYADARSHI ,  Rami Mohammad AL SHEIKH ,  Raguram DAMODARAN

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3804 ,  G06F9/3802 ,  G06F9/3844 ,  G06F12/0875 ,  G06F2212/452

Abstract: Systems and methods relate to an instruction fetch unit of a processor, such as a superscalar processor. The instruction fetch unit includes a fetch bandwidth predictor (FBWP) configured to predict a number of instructions to be fetched in a fetch group of instructions in a pipeline stage of the processor. A first entry of the FBWP corresponding to the fetch group corresponds to a prediction of the number of instructions to be fetched, based on occurrence and location of a predicted taken branch instruction in the fetch group and a confidence level associated with the predicted number in the prediction field. The instruction fetch unit is configured to fetch only the predicted number of instructions, rather than the maximum number of entries that can be fetched in the pipeline stage, if the confidence level is greater than a predetermined threshold. In this manner, wasteful fetching of instructions is avoided.

Abstract translation: 系统和方法涉及诸如超标量处理器的处理器的指令提取单元。 指令提取单元包括获取带宽预测器（FBWP），其被配置为预测将在处理器的流水线级中的取指令组中提取的指令数量。 对应于取出组的FBWP的第一条目对应于基于取出组中预测的分支指令的出现和位置以及与所提取的预测数相关联的置信水平的待提取的指令数量的预测 预测领域。 如果置信水平大于预定阈值，则指令提取单元被配置为仅获取预测数量的指令，而不是在流水线级中可以获取的最大条目数。 以这种方式，避免了浪费的指令提取。