公开(公告)号：US20250119059A1

公开(公告)日：2025-04-10

申请号：US18481657

申请日：2023-10-05

Applicant: Qualcomm Incorporated

Inventor： Boris Dimitrov ANDREEV ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Yong XU ,  Satish KRISHNAMOORTHY

IPC: H02M3/04 ,  H04W52/02

Abstract: In some aspects, an electronic device may detect a start of a voltage ramp transition period associated with changing a voltage at which an integrated circuit operates from a first voltage to a second voltage, wherein changing the voltage from the first voltage to the second voltage causes changes to one or more parameters that impact performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may trigger, responsive to detecting the start of the voltage ramp transition period, a dynamic calibration mode that compensates for the changes to the one or more parameters that impact the performance associated with the integrated circuit during the voltage ramp transition period. The electronic device may exit the dynamic calibration mode responsive to detecting an end of the voltage ramp transition period. Numerous other aspects are described.

公开(公告)号：US20240144980A1

公开(公告)日：2024-05-02

申请号：US17973996

申请日：2022-10-26

Applicant: QUALCOMM Incorporated

Inventor： Levon MSRYAN ,  Tigran MELIKYAN ,  Ashwin SETHURAM ,  Satish KRISHNAMOORTHY

IPC: G11C5/14 ,  H03K19/094

CPC classification number: G11C5/148 ,  G11C5/145 ,  G11C5/147 ,  H03K19/09429

Abstract: A transmitter circuit includes a first driver circuit configured to drive an input/output pad in an integrated circuit device, the first driver circuit including a thin-oxide transistor configured to couple the input/output pad to a first voltage rail when the transmitter circuit is operated in a first mode; a gate pullup transistor configured to couple a gate of the thin-oxide transistor to a second voltage rail when voltage of a third voltage rail is collapsed to a zero-volt level; and a switch configured to block transmission of a gating signal to the gate of the thin-oxide transistor when the voltage of the third voltage rail is collapsed to the zero-volt level.

公开(公告)号：US20220416536A1

公开(公告)日：2022-12-29

申请号：US17357239

申请日：2021-06-24

Applicant: QUALCOMM Incorporated

Inventor： Satish KRISHNAMOORTHY ,  Young Uk YIM ,  Ashwin SETHURAM

IPC: H02H9/02

Abstract: An ESD protection circuit in an interface circuit has a first diode coupled between a first power source of an integrated circuit device and an input/output pad of the integrated circuit device, a second diode coupled between a second power source of the integrated circuit device and the input/output pad, and a resistive element that couples the second diode to the first diode and to the input/output pad. The first power source supplies a driver circuit coupled to the input/output pad. The second power source supplies one or more core circuits of the integrated circuit device. The resistive element may be implemented as an interconnect configured to provide a resistance that produces a voltage differential between a terminal of the second diode and a corresponding terminal of the first diode during an electrostatic discharge event.

公开(公告)号：US20230275424A1

公开(公告)日：2023-08-31

申请号：US18312462

申请日：2023-05-04

Applicant: QUALCOMM Incorporated

Inventor： Satish KRISHNAMOORTHY ,  Young Uk YIM ,  Ashwin SETHURAM

IPC: H02H9/02 ,  H01L27/02

CPC classification number: H02H9/02 ,  H01L27/0255 ,  H01L27/0292

Abstract: An ESD protection circuit in an interface circuit has a first diode coupled between a first power source of an integrated circuit device and an input/output pad of the integrated circuit device, a second diode coupled between a second power source of the integrated circuit device and the input/output pad, and a resistive element that couples the second diode to the first diode and to the input/output pad. The first power source supplies a driver circuit coupled to the input/output pad. The second power source supplies one or more core circuits of the integrated circuit device. The resistive element may be implemented as an interconnect configured to provide a resistance that produces a voltage differential between a terminal of the second diode and a corresponding terminal of the first diode during an electrostatic discharge event.

公开(公告)号：US20200235737A1

公开(公告)日：2020-07-23

申请号：US16743872

申请日：2020-01-15

Applicant: QUALCOMM Incorporated

Inventor： Young Uk YIM ,  Jacob SCHNEIDER ,  Satish KRISHNAMOORTHY ,  Ashwin SETHURAM ,  Chang Ki KWON ,  Mostafa Naguib ABDULLA

IPC: H03K19/003 ,  H03K19/017 ,  G06F3/06

Abstract: A hybrid output data path is provided that supports high-voltage signaling and low-voltage signaling. The high-voltage signaling is powered by a high-power supply voltage that is greater than a low-power supply voltage that powers the low-voltage signaling.

公开(公告)号：US20240105243A1

公开(公告)日：2024-03-28

申请号：US17954852

申请日：2022-09-28

Applicant: QUALCOMM Incorporated

Inventor： Yong XU ,  Satish KRISHNAMOORTHY ,  Boris Dimitrov ANDREEV ,  Patrick ISAKANIAN ,  Farrukh AQUIL ,  Vikas MAHENDIYAN ,  Ravindra Arvind KHEDKAR

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/14

CPC classification number: G11C7/222 ,  G11C7/1066 ,  G11C7/14

Abstract: A memory interface circuit has a first differential receiver having a first input coupled to a first reference voltage source, a second differential receiver configured to receive a differential data strobe signal in a pair of complementary signals, a third differential receiver having a first input coupled to a second reference voltage source and a second input configured to receive one of the pair of complementary signals, a clock generation circuit configured to generate a read clock signal based on an output of the second differential receiver and using a qualifying signal output by the third differential receiver to qualify one or more edges in the read clock signal and a data capture circuit clocked by the read clock signal and configured to capture data from the output of the first differential receiver using the one or more edges in the read clock signal.

公开(公告)号：US20220393679A1

公开(公告)日：2022-12-08

申请号：US17804383

申请日：2022-05-27

Applicant: QUALCOMM Incorporated

Inventor： Patrick ISAKANIAN ,  Satish KRISHNAMOORTHY

IPC: H03K17/687 ,  G01R31/28 ,  H03K19/0185 ,  H03K5/24

Abstract: An aspect relates to an apparatus including a set of one or more receivers; a first replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a first control circuit generates an output signal selectively coupled to an input of the first replica circuit; a second replica circuit being a substantial replica of at least a portion of one of the set of one or more receivers; a comparator including a first input coupled to a first output of the first replica circuit, a second input coupled to a second output of the second replica circuit, and an output; and a second control circuit including an input coupled to the output of the comparator, and an output coupled to the first replica circuit and to the set of one or more receivers.