HIGH-SPEED LOW-POWER LEVEL-SHIFTING CLOCK BUFFER

    公开(公告)号:US20200028495A1

    公开(公告)日:2020-01-23

    申请号:US16516114

    申请日:2019-07-18

    Inventor: Tongyu SONG

    Abstract: A DC-coupled buffer is provided with two switch transistors controlled by a delayed version of an output signal for the DC-coupled buffer. A first one of the switch transistors functions to cut off a current discharged into ground that would otherwise flow while an input signal for the DC-coupled buffer is discharged. A remaining second one of the switch transistors functions to increase the operating speed of the DC-coupled buffer.

    RESIDUAL ERROR SAMPLING AND CORRECTION CIRCUITS IN INL DAC CALIBRATIONS
    3.
    发明申请
    RESIDUAL ERROR SAMPLING AND CORRECTION CIRCUITS IN INL DAC CALIBRATIONS 有权
    INL DAC校准中的残留误差采样和校正电路

    公开(公告)号:US20150318863A1

    公开(公告)日:2015-11-05

    申请号:US14609383

    申请日:2015-01-29

    CPC classification number: H03M1/1047 H03M1/1057 H03M1/68 H03M1/742

    Abstract: In an aspect of the disclosure, a method and an apparatus are provided for calibrating a DAC. The apparatus calibrates a first DAC element, provides a residual current error resulting from the calibration, the residual current error being a difference between a calibrated current source of the first DAC element and a reference current source, stores the residual current error of the calibrated first DAC element in a first memory module using at least first and second storage elements coupled to a differential amplifier, and calibrates a second DAC element using the stored residual current error.

    Abstract translation: 在本公开的一方面,提供了一种用于校准DAC的方法和装置。 该装置校准第一DAC元件,提供由校准导致的剩余电流误差,剩余电流误差是第一DAC元件的校准电流源与参考电流源之间的差,存储校准的第一个 DAC元件,其使用至少第一和第二存储元件耦合到差分放大器,并且使用所存储的剩余电流误差来校准第二DAC元件。

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