公开(公告)号：US20250088194A1

公开(公告)日：2025-03-13

申请号：US18463812

申请日：2023-09-08

Applicant: QUALCOMM Incorporated

Inventor： Vinay JAIN ,  Sunil Babu JAVAJI ,  Shat PRATEEK

IPC: H03L7/085 ,  H03L7/081 ,  H03L7/18 ,  H03M1/12

Abstract: An apparatus, including: a first synchronizer configured to synchronize a frequency divider reset signal with a reference clock signal to generate a reference clock domain reset signal; a set of delay buffers configured to generate a set of delayed staggered reference clock domain reset signals based on the reference clock domain reset signal; a set of second synchronizers configured to synchronize the set of delayed staggered reference clock domain reset signals with a phase lock loop (PLL) clock signal to generate a set of PLL clock domain reset signals; a phase detector configured to generate a signal related to a phase difference between respective clocking edges of the reference clock signal and the PLL clock signal; a phase corrector configured to generate a select signal based on the phase difference signal; and a multiplexer configured to output one of the PLL clock domain reset signals based on the select signal.

公开(公告)号：US20190236042A1

公开(公告)日：2019-08-01

申请号：US16219698

申请日：2018-12-13

Applicant: QUALCOMM Incorporated

Inventor： Helena Deirdre O'SHEA ,  Lalan Jee MISHRA ,  Amit GIL ,  Gary CHANG ,  Mohit Kishore Prasad ,  Richard Dominic WIETFELDT ,  Vinay JAIN

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/404 ,  G06F13/4022 ,  G06F13/4031 ,  G06F13/4291 ,  G06F2213/0052 ,  G06F2213/36

Abstract: In a device comprising a serial bus and a plurality of devices, register/address mappings and/or unique group identifiers are used to convey additional information in messages/datagrams over the serial bus without explicitly sending such information in the message/datagram. Such register/address mappings may be done beforehand, and in conjunction with group-specific identifiers, may reduce transmission latency by keeping the size of the messages/datagrams small. Since all devices on the serial bus have prior knowledge of such register/address mappings and/or group-specific identifiers, recipient devices are able to infer information from the group-specific identifiers and/or register/address sent in each message/datagram that is not explicitly sent within such message/datagram.