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    COLLABORATIVE BUS ARBITRATION MULTIPLEX ARCHITECTURE AND METHOD OF ARBITRATION OF DATA ACCESS BASED ON THE ARCHITECTURE
    2.
    发明申请
    COLLABORATIVE BUS ARBITRATION MULTIPLEX ARCHITECTURE AND METHOD OF ARBITRATION OF DATA ACCESS BASED ON THE ARCHITECTURE 有权
    协同总线仲裁多架构架构和基于架构的数据访问仲裁方法

    公开(公告)号：US20130254449A1

    公开(公告)日：2013-09-26

    申请号：US13474426

    申请日：2012-05-17

    Applicant: Sung-Jung WANG

    Inventor： Sung-Jung WANG

    IPC: G06F13/28 ,  G06F13/36

    CPC classification number: G06F13/28 ,  G06F2213/2802 ,  G06F2213/36 ,  G06F2213/28

    Abstract: A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting whether any of the BMPDs renders any request for access; B) identifying whether the access authority of the bus is being fetched by any other BMPDs; C) identifying whether the main memory to which the request for access corresponds have any record that the corresponding BMPD needs special treatment; D) identifying whether all of the BMPDs have rendered the requests for access; E) according to a generic arbitration principle, identifying whether the corresponding BMPDs indicated in the steps C) and D) win the access authority; F) yielding the access authority of the bus to the BMPDs winning the access authority as indicated in the step E); and G) accessing the main memory.

    Abstract translation: 协同总线仲裁多路复用架构包括主存储器，总线，多个BMPD和BAM。 可以按照以下步骤完成仲裁：等待任何BMPD是否提出访问请求; B）确定总线的访问权限是否由任何其他BMPD获取; C）确定访问请求对应的主存储器是否具有相应BMPD需要特殊处理的任何记录; D）确定所有的BMPD是否都提交了访问请求; E）根据通用仲裁原则，确定步骤C）和D）中指示的相应BMPD是否赢得访问权限; F）产生公共汽车对获得权限的BMPD的访问权限，如步骤E）所示; 和G）访问主存储器。

    ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT
    3.
    发明申请
    ARBITRATING BUS TRANSACTIONS ON A COMMUNICATIONS BUS BASED ON BUS DEVICE HEALTH INFORMATION AND RELATED POWER MANAGEMENT 审中-公开
    根据总线设备健康信息和相关电源管理对通信总线进行总线交易

    公开(公告)号：US20150234761A1

    公开(公告)日：2015-08-20

    申请号：US14706203

    申请日：2015-05-07

    Applicant: QUALCOMM Incorporated

    Inventor： Cristian Duroiu ,  Jaya Prakash Subramaniam Ganasan ,  Vinod Chamarty ,  Mark Michael Schaffer ,  Joshua Hirsch Stubbs ,  Robert Nicholson Gibson ,  Kris Tiri ,  Moinul Khan ,  Bohuslav Rychlik ,  Serag GadelRab ,  Simon Booth

    IPC: G06F13/37 ,  G06F13/16 ,  G06F13/18 ,  G06F13/42

    CPC classification number: G06F13/37 ,  G06F13/1626 ,  G06F13/18 ,  G06F13/362 ,  G06F13/4256 ,  G06F2213/0038 ,  G06F2213/0062 ,  G06F2213/0064 ,  G06F2213/36 ,  Y02D10/14

    Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

    Abstract translation: 公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。 主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。 在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。 总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。 总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。 总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

    METHOD AND APPARATUS USING HIGH-EFFICIENCY ATOMIC OPERATIONS
    4.
    发明申请
    METHOD AND APPARATUS USING HIGH-EFFICIENCY ATOMIC OPERATIONS 审中-公开
    使用高效率原子操作的方法和装置

    公开(公告)号：US20150234759A1

    公开(公告)日：2015-08-20

    申请号：US14425550

    申请日：2012-10-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： Zhixin Tian ,  Yunfeng He

    IPC: G06F13/364 ,  G06F13/22 ,  G06F13/16

    CPC classification number: G06F13/364 ,  G06F9/526 ,  G06F13/1652 ,  G06F13/1673 ,  G06F13/22 ,  G06F2213/1602 ,  G06F2213/36

    Abstract: A method of controlling access between multiple master devices to a shared resource is disclosed. The method includes receiving a request to access the shared resource from a first master device, and determining availability of the shared resource. If the shared resource is available, a successful response is returned to the first master device to establish access by the first master device to the shared resource. If the shared resource is unavailable, a failed response is returned to the first master device. During the resource's unavailability, it is automatically monitored for when the shared resource becomes available. Once available, the first master device is automatically notified.

    Abstract translation: 公开了一种控制多个主设备到共享资源之间的接入的方法。 该方法包括接收从第一主设备访问共享资源的请求，以及确定共享资源的可用性。 如果共享资源可用，则向第一主设备返回成功的响应，以建立第一主设备到共享资源的访问。 如果共享资源不可用，则将向第一个主设备返回失败的响应。 在资源不可用期间，将自动监视共享资源何时可用。 一旦可用，第一个主设备被自动通知。

    OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS
    6.
    发明申请
    OPTIMIZED CREDIT RETURN MECHANISM FOR PACKET SENDS 有权
    优化信用收益机制

    公开(公告)号：US20150378953A1

    公开(公告)日：2015-12-31

    申请号：US14316689

    申请日：2014-06-26

    Applicant: Intel Corporation

    Inventor： Mark Debbage ,  Yatin M. Mutha

    IPC: G06F13/42 ,  G06F13/16 ,  G06F13/28 ,  G06F13/362

    CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

    Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

    Abstract translation: 用于实现分组发送的优化信用回报机制的方法和装置。 编程输入/输出（PIO）发送存储器被划分成多个发送上下文，每个发送上下文包括一个存储器缓冲器，该存储器缓冲器包括被配置为存储分组数据的多个发送块。 使用FIFO语义的存储方案通过与相应的FIFO插槽相关联的每个发送块来实现。 响应于接收到写入发送块的分组数据并检测那些发送块中的数据已经从发送上下文中被发现，检测到相应的释放的FIFO时隙，并且确定没有返回信用返回标记的最低时隙。 然后确定从最低时隙的释放时隙序列中的最高时隙，并返回相应的信用回报标记。 在一个实施例中，对于每个发送上下文实现绝对信用回报计数，其中通过写入PIO发送存储器的软件跟踪相关联的绝对信用发送计数，其中两个绝对信用计数用于流量控制。

    Optimized credit return mechanism for packet sends
    10.
    发明授权
    Optimized credit return mechanism for packet sends 有权
    优化报文发送的信用回报机制

    公开(公告)号：US09477631B2

    公开(公告)日：2016-10-25

    申请号：US14316689

    申请日：2014-06-26

    Applicant: Intel Corporation

    Inventor： Mark Debbage ,  Yatin M. Mutha

    IPC: G06F13/36 ,  G06F13/42 ,  G06F13/362 ,  G06F13/28 ,  G06F13/12

    CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

    Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

    Abstract translation: 用于实现分组发送的优化信用回报机制的方法和装置。 编程输入/输出（PIO）发送存储器被划分成多个发送上下文，每个发送上下文包括一个存储器缓冲器，该存储器缓冲器包括被配置为存储分组数据的多个发送块。 使用FIFO语义的存储方案通过与相应的FIFO插槽相关联的每个发送块来实现。 响应于接收到写入发送块的分组数据并检测那些发送块中的数据已经从发送上下文中被发现，检测到相应的释放的FIFO时隙，并且确定没有返回信用返回标记的最低时隙。 然后确定从最低时隙的释放时隙序列中的最高时隙，并返回相应的信用回报标记。 在一个实施例中，对于每个发送上下文实现绝对信用回报计数，其中通过写入PIO发送存储器的软件跟踪相关联的绝对信用发送计数，其中两个绝对信用计数用于流量控制。

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