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公开(公告)号：US20180083584A1
公开(公告)日：2018-03-22
申请号：US15268264
申请日：2016-09-16
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Jacob Lee Dahle , Mangal Prasad , Joseph Natonio
CPC classification number: H03G1/007 , H03F3/45179 , H03G1/0023 , H03G1/0029 , H03G3/002 , H03G3/007 , H03G5/28
Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.
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公开(公告)号：US20190115908A1
公开(公告)日：2019-04-18
申请号：US15786976
申请日：2017-10-18
Applicant: QUALCOMM Incorporated
Inventor： Mangal Prasad , Victor Git-Han Moy , Xiaobin Yuan , Anirban Banerjee
CPC classification number: H03K5/26 , H03K3/0372 , H03K3/35625 , H03K19/20 , H03K23/54
Abstract: Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.
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公开(公告)号：US20170141735A1
公开(公告)日：2017-05-18
申请号：US14941366
申请日：2015-11-13
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Kevin Robert Bartholomew , Mangal Prasad
CPC classification number: H03G3/20 , H03F1/301 , H03F3/45197 , H03F3/45479 , H03F2203/45154 , H03F2203/45458 , H03F2203/45488 , H03F2203/45494 , H03G1/0023 , H03G1/0029 , H03G5/28 , H03K19/018514
Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
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公开(公告)号：US10396769B2
公开(公告)日：2019-08-27
申请号：US15786976
申请日：2017-10-18
Applicant: QUALCOMM Incorporated
Inventor： Mangal Prasad , Victor Git-Han Moy , Xiaobin Yuan , Anirban Banerjee
IPC: H03K5/26 , H03K19/20 , H03K3/037 , H03K23/54 , H03K3/3562
Abstract: Various clock frequency dividers are disclosed. Each frequency divider includes cascaded flip-flops and a feedback logic gate. First data inputs of the flip-flops are for propagating logic values along the cascaded flip-flops and the feedback gate for generating valid states of a sequence in response to a clock signal. Each frequency divider includes an invalid state elimination circuit configured to detect an invalid state at the outputs of the flip-flops and change it into a valid state in response to the clock signal. In some implementations, the invalid state elimination circuit includes a NOR gate to detect an all-zero invalid state and generate a control signal to cause the flip-flops to output logic values associated with a valid state or to cause a multiplexer to introduce a logic value associated with a valid state. In other implementations, the invalid state elimination circuit instead includes an AND gate to detect an all-ones invalid state.
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公开(公告)号：US09680418B2
公开(公告)日：2017-06-13
申请号：US14941366
申请日：2015-11-13
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Kevin Robert Bartholomew , Mangal Prasad
CPC classification number: H03G3/20 , H03F1/301 , H03F3/45197 , H03F3/45479 , H03F2203/45154 , H03F2203/45458 , H03F2203/45488 , H03F2203/45494 , H03G1/0023 , H03G1/0029 , H03G5/28 , H03K19/018514
Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
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Patent Agency Ranking
公开(公告)号：US20170085239A1
公开(公告)日：2017-03-23
申请号：US14857802
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Mangal Prasad , Joseph Natonio
CPC classification number: H03G3/3036 , H03F3/191 , H03F3/193 , H03F3/45197 , H03F2200/129 , H03F2200/372 , H03F2200/451 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45726 , H03H11/48 , H04B3/04 , H04L25/03878
Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.
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公开(公告)号：US10998720B2
公开(公告)日：2021-05-04
申请号：US15788650
申请日：2017-10-19
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Carrie Ellen Cox , Joseph Natonio , Siqi Fan
Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.
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8.发明申请公开(公告)号：US20190081604A1
公开(公告)日：2019-03-14
申请号：US15701072
申请日：2017-09-11
Applicant: QUALCOMM Incorporated
Inventor： Pradeep Thiagarajan , Xiaobin Yuan , Todd Morgan Rasmus
Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.
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公开(公告)号：US09755599B2
公开(公告)日：2017-09-05
申请号：US14857802
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Mangal Prasad , Joseph Natonio
CPC classification number: H03G3/3036 , H03F3/191 , H03F3/193 , H03F3/45197 , H03F2200/129 , H03F2200/372 , H03F2200/451 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45726 , H03H11/48 , H04B3/04 , H04L25/03878
Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.
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10.发明授权公开(公告)号：US10243531B1
公开(公告)日：2019-03-26
申请号：US15701072
申请日：2017-09-11
Applicant: QUALCOMM Incorporated
Inventor： Pradeep Thiagarajan , Xiaobin Yuan , Todd Morgan Rasmus
Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.
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