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公开(公告)号：US20180083584A1
公开(公告)日：2018-03-22
申请号：US15268264
申请日：2016-09-16
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Jacob Lee Dahle , Mangal Prasad , Joseph Natonio
CPC classification number: H03G1/007 , H03F3/45179 , H03G1/0023 , H03G1/0029 , H03G3/002 , H03G3/007 , H03G5/28
Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.
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公开(公告)号：US10998720B2
公开(公告)日：2021-05-04
申请号：US15788650
申请日：2017-10-19
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Carrie Ellen Cox , Joseph Natonio , Siqi Fan
Abstract: An Electro-Static Discharge (ESD) protection circuit is disclosed. In some implementations, the ESD protection circuit includes a first ESD diode, a second ESD diode, a passive equalization network and a programmable resistor network. The first ESD diode is coupled to the passive equalization network. The programmable resistor network is coupled between the passive equalization network and the second ESD diode. The programmable resistor network can be programmed to place the ESD protection circuit in one of a plurality of receiver modes based on a type of a transmitter from which the receiver is receiving signals.
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公开(公告)号：US09755599B2
公开(公告)日：2017-09-05
申请号：US14857802
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Mangal Prasad , Joseph Natonio
CPC classification number: H03G3/3036 , H03F3/191 , H03F3/193 , H03F3/45197 , H03F2200/129 , H03F2200/372 , H03F2200/451 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45726 , H03H11/48 , H04B3/04 , H04L25/03878
Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.
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公开(公告)号：US10027297B2
公开(公告)日：2018-07-17
申请号：US15268264
申请日：2016-09-16
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Jacob Lee Dahle , Mangal Prasad , Joseph Natonio
Abstract: One aspect of the present disclosure relates to a method for operating an amplifier, the amplifier including a variable resistor coupled between a source of a first input transistor and a source of a second input transistors, and a variable capacitor coupled between the source of the first input transistor and the source of the second input transistor. The method includes adjusting a resistance of the variable resistor to adjust a low-frequency gain of the amplifier, and adjusting a capacitance of the variable capacitor in an opposite direction as the adjustment to the resistance of the variable resistor.
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Patent Agency Ranking
5.发明授权公开(公告)号：US09647618B1
公开(公告)日：2017-05-09
申请号：US15084910
申请日：2016-03-30
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Mangal Prasad , Todd Morgan Rasmus
CPC classification number: H03G3/004 , H03F3/45197 , H03F3/45708 , H03F2200/411 , H03F2200/453 , H03F2200/456 , H03F2200/555 , H03F2203/45154 , H03F2203/45156 , H03F2203/45418 , H03G1/0023 , H03G1/0029 , H03G5/28
Abstract: The disclosure relates to a system and method for controlling a common mode voltage of an output differential signal of a differential signal processing circuit using a replica circuit and feedback control. The differential signal processing circuit includes two load devices, two input transistors, and two current-source transistors coupled in series between voltage rails, respectively. The replica circuit includes replica load device, replica input transistor, and replica current-source transistor coupled in series between the voltage rails. The common mode voltage of the input differential signal is applied to the replica input transistor to generate a replica output common mode voltage. A feedback circuit generates a bias voltage for the replica current-source transistor and the current-source transistors of the differential circuit to set and control the replica output common mode voltage and the output common mode voltage of the differential signal processing circuit to a target common mode voltage.
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公开(公告)号：US20170141735A1
公开(公告)日：2017-05-18
申请号：US14941366
申请日：2015-11-13
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Kevin Robert Bartholomew , Mangal Prasad
CPC classification number: H03G3/20 , H03F1/301 , H03F3/45197 , H03F3/45479 , H03F2203/45154 , H03F2203/45458 , H03F2203/45488 , H03F2203/45494 , H03G1/0023 , H03G1/0029 , H03G5/28 , H03K19/018514
Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
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公开(公告)号：US10135644B1
公开(公告)日：2018-11-20
申请号：US15691817
申请日：2017-08-31
Applicant: QUALCOMM Incorporated
Inventor： Todd Morgan Rasmus , Joseph Natonio
IPC: H04L25/03
Abstract: A low power 1-tap decision feedback equalizer (DFE) is disclosed. The DFE can include a plurality of AC-coupling networks, each having an input coupled to an output of a continuous time linear equalizer (CTLE) within an active stage of a receiver to receive a corresponding pair of differential signals of data, and an output coupled to a respective one of a plurality of data samplers to present a high frequency component of the corresponding pair of differential signals to the respective data sampler. The DFE can further include a plurality of transport paths, each transport path coupled to a respective AC-coupling network to receive the corresponding pair of differential signals. Each transport path can include one of the data sampler and an injection element to passively inject an offset into the high frequency component at an input of the respective data sampler.
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公开(公告)号：US09680418B2
公开(公告)日：2017-06-13
申请号：US14941366
申请日：2015-11-13
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Joseph Natonio , Kevin Robert Bartholomew , Mangal Prasad
CPC classification number: H03G3/20 , H03F1/301 , H03F3/45197 , H03F3/45479 , H03F2203/45154 , H03F2203/45458 , H03F2203/45488 , H03F2203/45494 , H03G1/0023 , H03G1/0029 , H03G5/28 , H03K19/018514
Abstract: A voltage gain amplifier (VGA) configured to have reduced supply noise. The VGA includes first resistor, first FET, and a first current-source coupled between first and second voltage rails. The VGA includes second resistor, second FET, and second current-source coupled between the voltage rails. A variable resistor is coupled between the respective sources of the first and second FETs. Variable capacitors are coupled between the first or a third voltage rail and the sources of the first and second input FETs, respectively. If capacitors are coupled to the first voltage rail, noise cancellation occurs across the gate-to-source voltages of the FETs if an input differential signal applied to the gates of the FETs is derived from a supply voltage at the first voltage rail. If capacitors are coupled to the third rail, supply noise is reduced if the supply voltage at the third rail is generated by a cleaner regulator.
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公开(公告)号：US20170085239A1
公开(公告)日：2017-03-23
申请号：US14857802
申请日：2015-09-17
Applicant: QUALCOMM Incorporated
Inventor： Xiaobin Yuan , Mangal Prasad , Joseph Natonio
CPC classification number: H03G3/3036 , H03F3/191 , H03F3/193 , H03F3/45197 , H03F2200/129 , H03F2200/372 , H03F2200/451 , H03F2203/45631 , H03F2203/45644 , H03F2203/45686 , H03F2203/45726 , H03H11/48 , H04B3/04 , H04L25/03878
Abstract: In one implementation, an amplifier comprises a load circuit comprising a plurality of inductor cells, and a drive circuit configured to receive an input signal, and to drive the load circuit based on the input signal to generate an amplified signal. The amplifier also comprises a controller configured to tune a peaking gain of the amplifier by adjusting a number of the inductor cells that are enabled.
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