公开(公告)号：US08877651B2

公开(公告)日：2014-11-04

申请号：US13326161

申请日：2011-12-14

申请人： Qiuhua Han ,  Xinpeng Wang ,  Yi Huang

发明人： Qiuhua Han ,  Xinpeng Wang ,  Yi Huang

IPC分类号： H01L21/306 ,  H01L21/768 ,  H01L29/78

CPC分类号： H01L21/76802 ,  H01L21/76832 ,  H01L21/76834

摘要： A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first silicon nitride layer and a second silicon nitride layer that is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion of the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.

摘要翻译： 一种制造半导体器件的方法包括在其上形成有栅极叠层的衬底的有源区上形成接触蚀刻停止层。 栅极堆叠包括金属栅极和金属氧化物。 接触蚀刻停止层包括夹在第一氮化硅层和设置在有源区上的第二氮化硅层之间的氧化硅层。 该方法还包括使用第一氮化硅层作为有源区的保护来形成延伸穿过第一氮化硅层上的层间电介质层的接触孔，去除设置在触点底部的第一氮化硅层的一部分 使用氧化硅层作为有源区的保护，并且使用第二氮化硅层去除金属氧化物作为有源区的保护。

公开(公告)号：US20130043516A1

公开(公告)日：2013-02-21

申请号：US13326161

申请日：2011-12-14

申请人： Qiuhua Han ,  Xinpeng Wang ,  Yi Huang

发明人： Qiuhua Han ,  Xinpeng Wang ,  Yi Huang

IPC分类号： H01L29/78 ,  H01L21/306

CPC分类号： H01L21/76802 ,  H01L21/76832 ,  H01L21/76834

摘要： A method for manufacturing a semiconductor device includes forming a contact etch stop layer on an active area of a substrate that has a gate stack formed thereon. The gate stack includes a metal gate and a metal oxide. The contact etch stop layer includes a silicon oxide layer sandwiched between a first and a silicon nitride layers, the second silicon nitride layer is disposed on the active area. The method further includes forming a contact hole extending through an interlayer dielectric layer on the first silicon nitride layer using the first silicon nitride layer as a protection for the active area, removing a portion the first silicon nitride layer disposed at the bottom of the contact hole using the silicon oxide layer as a protection for the active area, and removing the metal oxide using the second silicon nitride layer as a protection for the active area.

摘要翻译： 一种制造半导体器件的方法包括在其上形成有栅极叠层的衬底的有源区上形成接触蚀刻停止层。 栅极堆叠包括金属栅极和金属氧化物。 接触蚀刻停止层包括夹在第一和氮化硅层之间的氧化硅层，第二氮化硅层设置在有源区上。 该方法还包括通过使用第一氮化硅层作为有源区的保护来形成延伸穿过第一氮化硅层上的层间电介质层的接触孔，去除设置在接触孔底部的第一氮化硅层的一部分 使用氧化硅层作为有源区的保护，并且使用第二氮化硅层去除金属氧化物作为有源区的保护。

公开(公告)号：US09324662B2

公开(公告)日：2016-04-26

申请号：US13316165

申请日：2011-12-09

申请人： Xinpeng Wang ,  Yi Huang ,  Shih-Mou Chang

发明人： Xinpeng Wang ,  Yi Huang ,  Shih-Mou Chang

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/336 ,  H01L23/00 ,  H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L23/564 ,  H01L21/76801 ,  H01L21/76816 ,  H01L29/66575 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.

摘要翻译： 提供了一种半导体器件及其制造方法。 该方法包括：为半导体器件提供具有栅极结构的衬底和形成在其上的第一介电中间层，所述栅极结构包括金属栅极和所述第一介电中间层的上表面基本上与所述栅极的上表面齐平 ; 形成界面层以至少覆盖所述栅极的上表面，从而防止所述栅极的上表面被氧化; 以及在所述界面层上形成第二电介质中间层。

公开(公告)号：US20120292674A1

公开(公告)日：2012-11-22

申请号：US13458363

申请日：2012-04-27

申请人： Xinpeng Wang

发明人： Xinpeng Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L29/66545

摘要： A semiconductor device and method for manufacturing the same are provided. A substrate with an active area and a first interlayer dielectric formed over the substrate is provided. The first interlayer dielectric has a first opening exposing a portion of a surface of the active area, the first opening being filled with a fill material. A second interlayer dielectric is formed over the first interlayer dielectric with a second opening substantially exposing an upper portion of the fill material in the corresponding first opening. The fill material is then removed and the first opening and the second opening are filled with a conductive material to form a contact.

摘要翻译： 提供一种半导体器件及其制造方法。 提供了具有有源区的基板和形成在基板上的第一层间电介质。 第一层间电介质具有暴露有源区域的一部分表面的第一开口，第一开口填充有填充材料。 在第一层间电介质上形成第二层间电介质，其中第二开口基本上暴露在相应的第一开口中的填充材料的上部。 然后取出填充材料，并且用导电材料填充第一开口和第二开口以形成接触。

公开(公告)号：US08502289B2

公开(公告)日：2013-08-06

申请号：US13324945

申请日：2011-12-13

申请人： Xinpeng Wang ,  Haiyang Zhang

发明人： Xinpeng Wang ,  Haiyang Zhang

IPC分类号： H01L29/76

CPC分类号： H01L29/66795 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7855

摘要： The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.

摘要翻译： 本发明公开了一种双栅晶体管及其制造方法，所述晶体管包括：衬底上的半导体层; 在所述半导体层中形成的翅片结构，所述翅片结构具有用于形成源极和漏极区域的两个端部和用于形成沟道区域的所述两个端部之间的中间部分，所述中间部分包括垂直于衬底表面的两个相对的侧面 ; 第一栅极电介质层和设置在所述中间部分的一个侧表面上的第一栅极; 以及设置在所述中间部分的另一侧表面上的第二栅极电介质层和第二栅极。

公开(公告)号：US09111862B2

公开(公告)日：2015-08-18

申请号：US13431728

申请日：2012-03-27

申请人： Xinpeng Wang

发明人： Xinpeng Wang

IPC分类号： H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

摘要： A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate.

摘要翻译： 对半导体装置及其制造方法进行说明。 半导体装置包括衬底和用于衬底上方的N沟道半导体器件的栅极结构。 在栅极的两侧的至少一侧的下端部形成有与N沟道半导体的源极区域和漏极区域相邻的凹部。 N沟道半导体器件的沟道区域具有增强的应变。 该装置还可以在衬底上方具有用于P沟道半导体器件的栅极结构。

公开(公告)号：US08877577B2

公开(公告)日：2014-11-04

申请号：US13458363

申请日：2012-04-27

申请人： Xinpeng Wang

发明人： Xinpeng Wang

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L21/76895 ,  H01L21/76816 ,  H01L29/66545

摘要： A semiconductor device and method for manufacturing the same are provided. A substrate with an active area and a first interlayer dielectric formed over the substrate is provided. The first interlayer dielectric has a first opening exposing a portion of a surface of the active area, the first opening being filled with a fill material. A second interlayer dielectric is formed over the first interlayer dielectric with a second opening substantially exposing an upper portion of the fill material in the corresponding first opening. The fill material is then removed and the first opening and the second opening are filled with a conductive material to form a contact.

摘要翻译： 提供一种半导体器件及其制造方法。 提供了具有有源区的基板和形成在基板上的第一层间电介质。 第一层间电介质具有暴露有源区域的一部分表面的第一开口，第一开口填充有填充材料。 在第一层间电介质上形成第二层间电介质，其中第二开口基本上暴露在相应的第一开口中的填充材料的上部。 然后取出填充材料，并且用导电材料填充第一开口和第二开口以形成接触。

公开(公告)号：US08673776B2

公开(公告)日：2014-03-18

申请号：US13305417

申请日：2011-11-28

申请人： Xinpeng Wang

发明人： Xinpeng Wang

IPC分类号： H01L21/44

CPC分类号： H01L29/66545 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L29/78

摘要： A method for manufacturing a semiconductor device comprises: providing a substrate having an active area and a gate structure on the active area and formed with a first interlayer dielectric layer thereon, wherein the first interlayer dielectric layer has a first open to expose a portion of a surface of the active area, and an upper surface of the first interlayer dielectric layer is substantially flush with an upper surface of the gate; filling the first open with a first conductive material to form a first portion of contact; forming a second interlayer dielectric layer over the first interlayer dielectric layer, the second interlayer dielectric layer having a second open to substantially expose an upper part of the first portion of the contact in the first open; and filling the second open with a second conductive material to form a second portion of the contact.

摘要翻译： 一种制造半导体器件的方法包括：在有源区上提供具有有源区和栅极结构的衬底，并在其上形成有第一层间电介质层，其中第一层间介质层具有第一开口以暴露一部分 有源区的表面和第一层间电介质层的上表面与栅极的上表面基本齐平; 用第一导电材料填充第一开口以形成第一部分接触; 在所述第一层间介电层上形成第二层间介质层，所述第二层间介质层具有第二开口，以在所述第一开路中基本上暴露所述接触件的第一部分的上部; 并用第二导电材料填充第二开口以形成接触件的第二部分。

公开(公告)号：US20120292699A1

公开(公告)日：2012-11-22

申请号：US13431728

申请日：2012-03-27

申请人： Xinpeng Wang

发明人： Xinpeng Wang

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/7843 ,  H01L29/7847

摘要： A semiconductor apparatus and a manufacturing method therefor is described. The semiconductor apparatus comprises a substrate and a gate structure for a N-channel semiconductor device above the substrate. A recess is formed at a lower end portion of at least one of two sides of the gate where it is adjacent to a source region and a drain region, of the N-channel semiconductor. The channel region of the N-channel semiconductor device has enhanced strain. The apparatus can further have a gate structure for a P-channel semiconductor device above the substrate.

摘要翻译： 对半导体装置及其制造方法进行说明。 半导体装置包括衬底和用于衬底上方的N沟道半导体器件的栅极结构。 在栅极的两侧的至少一侧的下端部形成有与N沟道半导体的源极区域和漏极区域相邻的凹部。 N沟道半导体器件的沟道区域具有增强的应变。 该装置还可以在衬底上方具有用于P沟道半导体器件的栅极结构。