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1.发明公开公开(公告)号：US20240321707A1
公开(公告)日：2024-09-26
申请号：US18273464
申请日：2022-02-07
申请人： Qorvo US, Inc.
IPC分类号： H01L23/498 , H01L21/48
CPC分类号： H01L23/49838 , H01L21/4857 , H01L23/49894
摘要： Systems and methods of the present disclosure are directed to an electronic substrate. The electronic substrate includes a base layer, first feature(s) formed from a first metal layer and a second metal layer, and second feature(s) formed from the first metal layer. The electronic substrate includes a polymerized photodielectric layer over the first feature(s) and the second feature(s). The polymerized photodielectric layer exposes a portion of the second metal layer of the first feature(s), and at least a portion of the first metal layer of the second feature(s).
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公开(公告)号：US10796835B2
公开(公告)日：2020-10-06
申请号：US15208780
申请日：2016-07-13
申请人： Qorvo US, Inc.
发明人： Michael F. Zybura , George Maxim , Dirk Robert Walter Leipold , John August Orlowski , Baker Scott
摘要： Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.
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公开(公告)号：US10905007B1
公开(公告)日：2021-01-26
申请号：US16737319
申请日：2020-01-08
申请人： Qorvo US, Inc.
摘要： Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
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公开(公告)号：US20190385791A1
公开(公告)日：2019-12-19
申请号：US16555281
申请日：2019-08-29
申请人： Qorvo US, Inc.
IPC分类号： H01F41/04
摘要： This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.
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公开(公告)号：US10483035B2
公开(公告)日：2019-11-19
申请号：US15251647
申请日：2016-08-30
申请人： Qorvo US, Inc.
摘要： This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.
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公开(公告)号：US11596058B2
公开(公告)日：2023-02-28
申请号：US16383752
申请日：2019-04-15
申请人： Qorvo US, Inc.
摘要： Laminate structures and configurations of fiducials for laminates structures for electronic devices are disclosed. Fiducials are formed in laminate structures to provide increased visibility and contrast, thereby improving detection of the fiducials with optical detection equipment of automated machines commonly used in the electronics industry. Fiducials are disclosed that are defined by openings in laminate structures that extend to depths within the laminate structures to provide sufficient contrast. Openings for fiducials may be arranged to extend through multiple metal layers and dielectric layers of the laminate structures. The fiducials may be formed by laser drilling or other subtractive processing techniques. Fiducials as disclosed herein may be coated with additional layers or coatings, such as a metal coating that includes an electromagnetic shield for electronic devices, and the fiducials are configured with sufficient visibility and contrast to remain detectable through the additional layers or coatings.
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公开(公告)号：US20200288567A1
公开(公告)日：2020-09-10
申请号：US16383752
申请日：2019-04-15
申请人： Qorvo US, Inc.
摘要： Laminate structures and configurations of fiducials for laminates structures for electronic devices are disclosed. Fiducials are formed in laminate structures to provide increased visibility and contrast, thereby improving detection of the fiducials with optical detection equipment of automated machines commonly used in the electronics industry. Fiducials are disclosed that are defined by openings in laminate structures that extend to depths within the laminate structures to provide sufficient contrast. Openings for fiducials may be arranged to extend through multiple metal layers and dielectric layers of the laminate structures. The fiducials may be formed by laser drilling or other subtractive processing techniques. Fiducials as disclosed herein may be coated with additional layers or coatings, such as a metal coating that includes an electromagnetic shield for electronic devices, and the fiducials are configured with sufficient visibility and contrast to remain detectable through the additional layers or coatings.
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公开(公告)号：US20170084378A1
公开(公告)日：2017-03-23
申请号：US15251647
申请日：2016-08-30
申请人： Qorvo US, Inc.
摘要： This disclosure relates generally to substrates having three dimensional (3D) inductors and methods of manufacturing the same. In one embodiment, the 3D inductor is a solenoid inductor where the exterior edge contour of the winding ends is substantially the same and substantially aligned with the exterior edge contour of the exterior edge contour of conductive vias that connect the windings. In this manner, there is no overhang between the windings and the conductive vias. In another embodiment of the 3D inductor, via columns connect connector plates. The via column attachment surfaces of each of the conductive vias in each of the columns is the same and substantially aligned. In this manner, carrier pads are not needed and there is no overhand between the conductive vias.
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9.发明申请STACKED LAMINATE INDUCTORS FOR HIGH MODULE VOLUME UTILIZATION AND PERFORMANCE-COST-SIZE-PROCESSING-TIME TRADEOFF 审中-公开用于高模块体积利用和性能 - 成本 - 加工时间贸易的堆叠层压电感器公开(公告)号：US20170062119A1
公开(公告)日：2017-03-02
申请号：US15208780
申请日：2016-07-13
申请人： Qorvo US, Inc.
发明人： Michael F. Zybura , George Maxim , Dirk Robert Walter Leipold , John August Orlowski , Baker Scott
摘要： Embodiments of electronic devices, such as integrated circuit (IC) packages are disclosed. In one embodiment, an electronic device includes a first substrate and a second substrate. The first substrate has a first substrate body and a first inductor portion integrated into the first substrate body. Additionally, the second substrate comprises a second substrate body and a second inductor portion integrated into the second substrate body. The second substrate is mounted on the first substrate such that such that the second inductor portion is positioned over the first inductor portion and such that the second inductor portion is electrically connected to the first inductor portion so that the first inductor portion and the second inductor portion form a three dimensional (3D) inductor. By using two substrates, the 3D inductor can be increased in height while still allowing the substrates to be miniaturized and standardized for an IC package.
摘要翻译： 公开了诸如集成电路（IC）封装的电子设备的实施例。 在一个实施例中，电子设备包括第一基板和第二基板。 第一基板具有第一基板主体和集成到第一基板主体中的第一电感器部分。 另外，第二基板包括集成到第二基板主体中的第二基板主体和第二电感部分。 第二基板安装在第一基板上，使得第二电感器部分位于第一电感器部分上方，并且使得第二电感器部分电连接到第一电感器部分，使得第一电感器部分和第二电感器部分 形成三维（3D）电感器。 通过使用两个基板，3D电感器的高度可以增加，同时仍然允许基板小型化并且对于IC封装进行标准化。
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公开(公告)号：US11765826B2
公开(公告)日：2023-09-19
申请号：US17157294
申请日：2021-01-25
申请人： Qorvo US, Inc.
CPC分类号： H05K1/113 , H05K3/0041 , H05K3/243 , H05K3/4007 , H05K2201/09736
摘要： Electronic substrates, contact pads for electronic substrates, and related methods are disclosed. Electronic substrates may include an electrically conductive layer that forms at least one contact pad and at least one metal trace on a non-conductive layer. The contact pads are arranged with greater thicknesses or heights above the non-conductive layer than the metal traces. Dielectric layers are disclosed that cover the metal traces while leaving top surfaces of the contact pads exposed. Top surfaces of the dielectric layers may be arranged to be coplanar with top surfaces of the contact pads to provide electronic substrates having generally planar top faces. Bottom faces of electronic substrates may include mounting pads that are coplanar with additional dielectric layers. Methods are disclosed that include forming dielectric layers to cover contact pads and metal traces, and removing surface portions of the dielectric layers until the contact pads are accessible through the dielectric layers.
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