公开(公告)号：US20240298412A1

公开(公告)日：2024-09-05

申请号：US18325086

申请日：2023-05-29

Applicant: AAC Microtech (Changzhou) Co., Ltd.

Inventor： Guohui Chen

IPC: H05K3/24 ,  H05K1/02

CPC classification number: H05K3/243 ,  H05K1/0298 ,  H05K2203/068 ,  H05K2203/0723

Abstract: The present disclosure discloses a circuit board including a substrate layer and a conductive layer attached to one side of the substrate layer, the conductive layer being divided into a copper-plated area and a non-copper-plated area adjacent to the copper-plated area, the conductive layer having a greater thickness in the copper-plated area than in the non-copper-plated area, a boundary pattern being formed at the demarcation between the copper-plated area and the non-copper-plated area. In the direction from the non-copper-plated area toward the copper-plated area, the distance between the border pattern from the middle outward and the edge of the corresponding side of the non-copper-plated area gradually decreases. When the platen roller reaches the boundary pattern position, the air can be squeezed from the middle to both sides along the boundary pattern, thus reducing the air bubbles at the junction of copper-plated and non-copper-plated areas.

公开(公告)号：US20240206078A1

公开(公告)日：2024-06-20

申请号：US18207331

申请日：2023-06-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Youngkyun Oh

IPC: H05K3/24 ,  H05K1/11

CPC classification number: H05K3/243 ,  H05K1/111

Abstract: A circuit board according to an embodiment includes: an insulating layer; a conductive pad disposed on the insulating layer, a plating lead-in wire that is disposed on the insulating layer and is connected to the conductive pad; and a solder resist layer that is disposed on the insulating layer and includes a first opening overlapping the conductive pad and a second opening spaced apart from the first opening. The plating lead-in wire extends from the conductive pad to one side wall of the second opening, and a second portion of the insulating layer overlapping the second opening is thinner than a first portion of the insulating layer overlapping the first opening.

公开(公告)号：US10076800B2

公开(公告)日：2018-09-18

申请号：US14954243

申请日：2015-11-30

Applicant: Cree Fayetteville, Inc.

Inventor： Jennifer Stabach ,  Brice McPherson ,  Chad B. O'Neal

IPC: B23K31/02 ,  B23K1/20 ,  B23K1/00 ,  B23K26/362 ,  H01L23/13 ,  H05K3/02 ,  H05K1/02 ,  H05K3/24 ,  H05K3/34

CPC classification number: B23K1/20 ,  B23K1/0016 ,  B23K26/361 ,  B23K26/362 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/49894 ,  H01L2224/32225 ,  H05K1/0263 ,  H05K3/027 ,  H05K3/243 ,  H05K3/341 ,  H05K2201/09363 ,  H05K2203/0315 ,  H05K2203/1173

Abstract: A process for manufacturing an electronic component having attaches includes providing a first component having a first attach, forming trenches on a portion of the first attach with a laser to form a solder stop, and providing a second component comprising a second attach. The process further includes providing solder between the first attach and the second attach to form a connection between the first component and the second component, where the trenches contain the solder to a usable area. A device produced by the process is disclosed as well.

公开(公告)号：US09918378B1

公开(公告)日：2018-03-13

申请号：US15784296

申请日：2017-10-16

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tomoyuki Shimodaira

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/09 ,  H01L21/48

CPC classification number: H05K1/0213 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/49866 ,  H05K1/09 ,  H05K3/243 ,  H05K3/3473 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/0465

Abstract: A wiring substrate includes a wiring layer, an insulating layer covering the wiring layer, and a protruding electrode including a protruding metal layer and a surface metal layer. The protruding metal layer is connected to the wiring layer in an opening of the insulating layer, extends from within the opening to be stepped at the edge of the opening to extend outward onto the insulating layer, and includes a first surface contacting a surface of the insulating layer around the opening, a second surface, and a peripheral surface extending between the first and second surfaces, and bent inward to form a space between the peripheral surface and the surface of the insulating layer. The surface metal layer covers the protruding metal layer without contacting the surface of the insulating layer, and is formed of a metal having a lower melting point than the protruding metal layer.

公开(公告)号：US20180054890A1

公开(公告)日：2018-02-22

申请号：US15682721

申请日：2017-08-22

Applicant: IBIDEN CO., LTD.

Inventor： Teruyuki ISHIHARA ,  Hiroyuki BAN ,  Haiying MEI

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18 ,  H05K3/02 ,  H05K3/06 ,  H05K3/46 ,  H05K3/40

CPC classification number: H05K1/113 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/181 ,  H05K3/025 ,  H05K3/06 ,  H05K3/243 ,  H05K3/284 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/0338 ,  H05K2201/10378 ,  Y02P70/611

Abstract: A printed wiring board includes a support plate, a laminate formed on the support plate and including first conductor pads on first surface side of the laminate and first via conductors on second surface side of the laminate, and a solder resist layer interposed between the plate and the laminate and having openings formed such that the openings are exposing the first pads. The laminate has first surface on the first surface side and second surface on the second surface side on the opposite side and includes a first resin insulating layer forming the second surface of the laminate, and the first conductors are formed through the first insulating layer such that the first vias are tapering from the first surface side toward the second surface side of the laminate and have end surfaces recessed from the second surface of the laminate on the second surface side of the laminate.

公开(公告)号：US09883589B2

公开(公告)日：2018-01-30

申请号：US14764795

申请日：2014-07-30

Applicant: KYOCERA Corporation

Inventor： Kouichi Kawasaki

IPC: H05K7/10 ,  H05K1/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H05K3/34 ,  H05K1/18 ,  H05K1/02 ,  H01R9/00 ,  H01L23/48 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K1/111 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49838 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3431 ,  H05K3/4629 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09663 ,  H05K2201/097 ,  H05K2201/098 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/2054 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A wiring board has an insulation base plate, and a plurality of electrodes provided adjacent to each other in plan view on the insulation base plate, the electrodes have an opening in the outer periphery and a slit oriented from the outer periphery to the interior, and, among two electrodes adjacent to each other, the slit in one electrode has a central line intersecting the outer periphery of the other electrode.

公开(公告)号：US09693453B2

公开(公告)日：2017-06-27

申请号：US14019863

申请日：2013-09-06

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Takahiro Hayashi ,  Seiji Mori ,  Tatsuya Ito

IPC: H05K1/00 ,  H05K1/09 ,  H01L23/00 ,  H05K3/28 ,  H05K3/40 ,  H01L21/56 ,  H05K3/24

CPC classification number: H05K1/092 ,  H01L21/563 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/13101 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81455 ,  H01L2224/92125 ,  H05K3/243 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0769 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/0597 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A wiring board includes a base layer, a plurality of connection terminals and a surface layer. The base layer is electrically insulative. The plurality of connection terminals are conductive and formed on the base layer. The surface layer is electrically insulative, and fills gaps between the plurality of connection terminals on the base layer. The connection terminals include a base portion made of a conductive first metal and a coating portion made of a conductive second metal that is different from the first metal. The coating portion penetrates the surface layer, and coats the base portion to the base layer.

公开(公告)号：US09668340B1

公开(公告)日：2017-05-30

申请号：US15139122

申请日：2016-04-26

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Jack Ajoian ,  Lea-Teng Lee

IPC: H05K1/00 ,  H05K1/02 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K1/09 ,  H05K3/06 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H05K1/09 ,  H05K3/243 ,  H05K3/4007 ,  H05K2201/0338 ,  H05K2201/0376

Abstract: A build-up process for fabricating a multi-layer PCB is provided that prevents, or at least reduces the lengths of, overhangs in the finishing metal layer that is plated onto the electrical contact metal layer. The metal seed layer is etched away prior to plating the finishing metal layer onto the electrical contact metal layer. The electrical contact metal layer is covered with a layer of dielectric material, which is then patterned to selectively expose preselected areas of the electrical contact metal layer. The exposed preselected areas of the electrical contact metal layer are then plated with the finishing layer of metal. The result is that overhangs are eliminated or at least greatly reduced in length. In addition, the dielectric material layer serves a function similar to that of a solder mask and obviates the need to apply the oxide to serve as a solder mask.

公开(公告)号：US09622340B2

公开(公告)日：2017-04-11

申请号：US14858953

申请日：2015-09-18

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： Xian-Qin Hu ,  Yan-Lu Li ,  Wen-Hsin Yu ,  Ming-Jaan Ho

IPC: H05K3/28 ,  H05K1/02 ,  H05K3/10

CPC classification number: H05K1/0228 ,  H05K1/0221 ,  H05K1/0237 ,  H05K1/0242 ,  H05K1/028 ,  H05K1/0393 ,  H05K3/10 ,  H05K3/243 ,  H05K3/28 ,  H05K3/281 ,  H05K2201/0355 ,  H05K2201/0715

Abstract: A flexible circuit board includes an insulating layer, a linear signal line, a plurality of grounding lines, a metal coating layer, a circuit layer and an electromagnetic shielding layer. The insulating layer includes a first face and a second face. The metal coating layer covers the linear signal line on the first face. The metal coating layer has a thickness less than that of the linear signal line, and an electrical conductivity larger than that of the linear signal line. The grounding lines are at two opposite sides of the linear signal line on the first face. The circuit layer is on the second face. The electromagnetic shielding layer covers the linear signal line and the grounding lines. The linear signal line and the grounding lines are between the electromagnetic shielding layer and the circuit layer. A method for manufacturing the flexible circuit board is also provided.

公开(公告)号：US09609752B1

公开(公告)日：2017-03-28

申请号：US14213833

申请日：2014-03-14

Applicant: Lockheed Martin Corporation

Inventor： Daniel L. Blass ,  Jack V. Ajoian

IPC: H05K1/00 ,  H05K1/14

CPC classification number: H05K1/141 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/10175 ,  H01L2224/13611 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81455 ,  H01L2224/81815 ,  H05K1/111 ,  H05K3/243 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2203/0315 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

Abstract: An interconnect structure and method for manufacturing the same includes a substrate and a copper trace line defined on a surface of the substrate. The copper trace line includes a transmission line and a contact pad. The copper trace line is plated with a layer of metal which will oxidize if exposed to the atmosphere. The layer of metal is further plated with a layer of gold. The gold layer is selectively applied to the transmission line and the contact pad to define a gap on the transmission line at the contact pad. The metal layer is exposed in the gap. An oxide layer is formed on the metal layer in the gap. The oxide layer and the substrate surround the contact pad define a barrier to spread of solder.