Apparatus, system and method for autonomous recovery from failures during system characterization on an environment with restricted resources
    2.
    发明授权
    Apparatus, system and method for autonomous recovery from failures during system characterization on an environment with restricted resources 有权
    在资源有限的环境下系统表征期间自动恢复故障的装置,系统和方法

    公开(公告)号:US09251006B2

    公开(公告)日:2016-02-02

    申请号:US14139704

    申请日:2013-12-23

    IPC分类号: G06F11/00 G06F11/14 G06F11/22

    摘要: A power management mechanism maintains power to a processor and an integrated memory. Read-only logic and a cache are also provided. At power on, the read-only logic configures the cache as an internal memory and loads executable instructions in the cache. A copy of the executable instructions is stored in the internal memory. A branch instruction is also stored. Thereafter, the processor uses the copy of the executable instructions and present status information. The processor is programmed to issue a reset signal when a failure is detected. The read-only logic responds to the reset signal by going to the branch instruction in the internal memory, which directs the processor to use the copy of the executable instructions and status information in the internal memory circuit. The operating state is restored and the processor is instructed to execute the next instruction in the copy of executable instructions.

    摘要翻译: 电源管理机构维持处理器和集成存储器的电源。 还提供只读逻辑和缓存。 上电时,只读逻辑将高速缓存配置为内部存储器,并在缓存中加载可执行指令。 可执行指令的副本存储在内部存储器中。 还存储分支指令。 此后,处理器使用可执行指令的副本并呈现状态信息。 处理器被编程为在检测到故障时发出复位信号。 只读逻辑通过转到内部存储器中的分支指令来响应复位信号,这引导处理器使用内部存储器电路中的可执行指令和状态信息的副本。 恢复操作状态,并指示处理器执行可执行指令副本中的下一条指令。

    Partitioning flash and enabling flexible boot with image upgrade capabilities

    公开(公告)号:US10915331B2

    公开(公告)日:2021-02-09

    申请号:US15669257

    申请日:2017-08-04

    摘要: Various aspects include methods for implementing a reduced size firmware storage format on a computing device. Various aspects may include storing a first firmware description table to a first sector of a flash memory, in which the first firmware description table may define a first instance of a firmware including describing a first plurality of firmware images, storing the first plurality of firmware images to a first plurality of consecutive sectors, storing a second firmware description table to a second sector, in which the second firmware description table may define a second instance of the firmware including describing a second plurality of firmware images having a third plurality of firmware images, storing the third plurality of firmware images to a second plurality of consecutive sectors, and booting the computing device using the second firmware description table.

    System and method for modifying a sequence of instructions in a read-only memory of a computing device
    4.
    发明授权
    System and method for modifying a sequence of instructions in a read-only memory of a computing device 有权
    用于修改计算设备的只读存储器中的指令序列的系统和方法

    公开(公告)号:US09547489B2

    公开(公告)日:2017-01-17

    申请号:US14307415

    申请日:2014-06-17

    IPC分类号: G06F9/00 G06F9/445 G06F21/57

    CPC分类号: G06F8/66 G06F21/575

    摘要: A system and method for patching a boot sequence in a read-only memory. Patch instances are provided in an addressable memory. The patch instances are initially empty. The read-only memory includes a process that dynamically vectors to identified locations in a set of addressable memory locations in the addressable memory. Thereafter, the process returns to the next subsequent instruction following the patch instance. As corrections are required, the one or more patch instances are populated with one or more respective patches. The boot sequence is modified by inserting one or more patch indicators located where patches might need to be applied after a system-on-chip (SoC) is embodied in firmware. The patches, when defined, are populated with at least an encoded instruction type and an address. Accordingly, a patch is enabled in no more than three words.

    摘要翻译: 用于在只读存储器中修补引导序列的系统和方法。 补丁实例在可寻址存储器中提供。 补丁实例最初为空。 只读存储器包括动态地向可寻址存储器中的一组可寻址存储器位置中的识别位置传送的过程。 此后,该过程返回到补丁实例之后的下一个后续指令。 当需要更正时,一个或多个补丁实例被填充有一个或多个相应的补丁。 通过在固件中体现片上系统(SoC)之后插入一个或多个补丁指示器来修改引导顺序,该补丁指示器位于需要应用补丁的位置。 补丁在定义时至少填充一个编码指令类型和地址。 因此,补丁的启用不超过三个字。

    Multithread framework for use in pre-boot environment of a system-on-chip

    公开(公告)号:US10802875B2

    公开(公告)日:2020-10-13

    申请号:US16203386

    申请日:2018-11-28

    摘要: Various aspects are described herein. In some aspects, the disclosure provides a method for a system-on-chip (SoC) including one or more computing cores. The method includes providing a scheduler to schedule running of threads on the one or more computing cores in a pre-boot environment including a core thread configured to provide a plurality of services. The method further includes providing, by the scheduler, a first lock for the core thread. The method further includes initializing, by the core thread, one or more additional services separate from the plurality of services. The method further includes selectively allowing access to the plurality of services of the core thread to one or more additional threads based on a status of the first lock. The method further includes allowing access to the one or more additional services to the one or more additional threads independent of the status of the first lock.

    SYSTEM AND METHOD FOR MODIFYING FIRMWARE USED TO INITIALIZE A COMPUTING DEVICE

    公开(公告)号:US20170123788A1

    公开(公告)日:2017-05-04

    申请号:US15400925

    申请日:2017-01-06

    IPC分类号: G06F9/445 G06F21/57

    CPC分类号: G06F8/66 G06F21/575

    摘要: A system and method for patching a boot sequence in a read-only memory. Patch instances are provided in an addressable memory. The patch instances are initially empty. The read-only memory includes a process that dynamically vectors to identified locations in a set of addressable memory locations in the addressable memory. Thereafter, the process returns to the next subsequent instruction following the patch instance. As corrections are required, the one or more patch instances are populated with one or more respective patches. The boot sequence is modified by inserting one or more patch indicators located where patches might need to be applied after a system-on-chip (SoC) is embodied in firmware. The patches, when defined, are populated with at least an encoded instruction type and an address. Accordingly, a patch is enabled in no more than three words.

    Virtual boundary codes in a data image of a read-write memory device
    7.
    发明授权
    Virtual boundary codes in a data image of a read-write memory device 有权
    读写存储器件的数据图像中的虚拟边界码

    公开(公告)号:US09442840B2

    公开(公告)日:2016-09-13

    申请号:US13720532

    申请日:2012-12-19

    IPC分类号: G06F12/02 G06F3/06 G11C29/00

    摘要: Methods, systems and devices are provided for configuring a read-write memory device with a data image. The method includes determining a data image distribution based on a virtual block size of a series of virtual blocks designated for the read-write memory device. The data image is divided into one or more data image portions, wherein a virtual boundary code is appended to at least one of the data image portions. The data image portions are stored in respective virtual blocks of the series of virtual blocks, skipping over any bad block within the read-write memory device, even between the virtual blocks.

    摘要翻译: 提供了用于配置具有数据图像的读写存储器件的方法,系统和设备。 该方法包括基于为读写存储器设备指定的一系列虚拟块的虚拟块大小确定数据映像分布。 数据图像被分成一个或多个数据图像部分,其中虚拟边界码被附加到数据图像部分中的至少一个。 数据图像部分存储在一系列虚拟块的相应虚拟块中,甚至在虚拟块之间跳过读写存储器设备内的任何坏块。

    Multicore framework for use in pre-boot environment of a system-on-chip

    公开(公告)号:US10860332B2

    公开(公告)日:2020-12-08

    申请号:US16137226

    申请日:2018-09-20

    摘要: Various aspects are described herein. In some aspects, the disclosure provides a method of enabling a multicore framework in a pre-boot environment for a system-on-chip (SoC) comprising a plurality of processors comprising a first processor and a second processor. The method includes initiating, by the first processor, bootup of the SoC into a pre-boot environment. The method further includes scheduling, by the first processor, execution of one or more boot-up tasks by a second processor. The method further includes executing, by the second processor, the one or more boot-up tasks in the pre-boot environment. The method further includes executing, by the first processor, one or more additional tasks in parallel with the second processor executing the one or more boot-up tasks.