公开(公告)号：US20170063092A1

公开(公告)日：2017-03-02

申请号：US14843983

申请日：2015-09-02

Applicant: QUALCOMM Incorporated

Inventor： Chunlei SHI ,  Yu PU ,  Kenneth David EASTON ,  Kendrick Hoy Leong YUEN ,  Giby SAMSON

IPC: H02J3/38

CPC classification number: H02J3/38 ,  G06F1/3287 ,  H02J2003/388 ,  H03K19/0016

Abstract: A switchable supply network for powering multiple digital islands. In one embodiment, a first digital island includes a first power collapsible circuit and a first retention circuit, and a second digital island includes a second power collapsible circuit and a second retention circuit. In a normal mode of operation, the first digital island is provided a first supply voltage and a second digital island is provided a second supply voltage higher than the first supply voltage. In a transition mode the second power collapsible circuit is powered down and the second supply voltage is lowered and provided to the second retention circuit. When the second supply voltage falls below the first supply voltage, the first power collapsible circuit is powered down. The second supply voltage is now provided only to the retention circuits, and is furthered lowered in a retention mode to a final retention voltage.

Abstract translation: 用于为多个数字岛供电的可切换供电网络。 在一个实施例中，第一数字岛包括第一电源可折叠电路和第一保持电路，第二数字岛包括第二电源可折叠电路和第二保持电路。 在正常操作模式中，第一数字岛被提供第一电源电压，并且第二数字岛被提供有高于第一电源电压的第二电源电压。 在转换模式中，第二功率可折叠电路断电并且第二电源电压降低并提供给第二保持电路。 当第二电源电压低于第一电源电压时，第一电源可折叠电路断电。 现在仅向保持电路提供第二电源电压，并且在保持模式下进一步降低到最终的保持电压。

公开(公告)号：US20220308653A1

公开(公告)日：2022-09-29

申请号：US17840265

申请日：2022-06-14

Applicant: QUALCOMM Incorporated

Inventor： Yu PU ,  Yang DU

IPC: G06F1/3287 ,  G06N3/04 ,  G06F1/3234 ,  G06F1/3296 ,  G06N3/063

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

公开(公告)号：US20190305683A1

公开(公告)日：2019-10-03

申请号：US15937947

申请日：2018-03-28

Applicant: QUALCOMM Incorporated

Inventor： Chunlei SHI ,  Jongrit LERDWORATAWEE ,  Yu PU

IPC: H02M3/158 ,  G05F1/26

Abstract: A boost and LDO hybrid converter with dual-loop control is disclosed. In some implementations, a hybrid converter includes an inductor having a first terminal to receive an input voltage and a second terminal; an n-type metal oxide semiconductor device (nMOS) having a drain coupled to the second terminal of the inductor; a p-type metal oxide semiconductor device (pMOS) having a gate, a drain, and a source, the source coupled to the second terminal of the inductor; an output capacitor having a first terminal coupled to the drain of the first pMOS; and a controller having a switch driver and a buffer, wherein the controller is configured to use the switch driver to drive the gate of the first pMOS in a boost mode and to use the buffer to drive the gate of the first pMOS in a low drop out (LDO) mode.

公开(公告)号：US20190073585A1

公开(公告)日：2019-03-07

申请号：US16119929

申请日：2018-08-31

Applicant: QUALCOMM Incorporated

Inventor： Yu PU ,  Yang DU

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: A three-dimensional (3D) ultra-low power neuromorphic accelerator is described. The 3D ultra-low power neuromorphic accelerator includes a power manager as well as multiple tiers. The 3D ultra-low power neuromorphic accelerator also includes multiple cores defined on each tier and coupled to the power manager. Each core includes at least a processing element, a non-volatile memory, and a communications module.

公开(公告)号：US20210225435A1

公开(公告)日：2021-07-22

申请号：US17223764

申请日：2021-04-06

Applicant: Qualcomm Incorporated

Inventor： Hoan Huu NGUYEN ,  Francois Ibrahim ATALLAH ,  Keith Alan BOWMAN ,  Daniel YINGLING ,  Jihoon JEONG ,  Yu PU

IPC: G11C11/417 ,  G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/418 ,  G11C11/419

Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.

公开(公告)号：US20170089974A1

公开(公告)日：2017-03-30

申请号：US15015547

申请日：2016-02-04

Applicant: QUALCOMM Incorporated

Inventor： Yu PU ,  Giby SAMSON ,  Kendrick Hoy Leong YUEN

IPC: G01R31/28

CPC classification number: G01R31/2851 ,  G01R31/2884 ,  G01R31/3004 ,  H01L22/14 ,  H01L22/34

Abstract: Methods and apparatus for identifying a process corner are provided. Provided is an exemplary method for identifying a process corner of an integrated circuit (IC). The IC has a first asymmetrical ring oscillator (ARO1) including pull-up transistors that have a low threshold voltage (LVT) and pull-down transistors that have a regular threshold voltage (RVT), and has a second asymmetrical ring oscillator (ARO2) including pull-up transistors that have an RVT and pull-down transistors having an LVT. The exemplary method includes applying an ultra-low power supply voltage to the ARO1 and the ARO2 that causes the integrated circuit to operate near a verge of malfunction, measuring an output frequency of the ARO1, measuring an output frequency of the ARO2, calculating a calculated ratio of the output frequency of the ARO1 and the output frequency of the ARO2, and comparing the calculated ratio to a fiduciary ratio to identify the process corner.