公开(公告)号：US20180069535A1

公开(公告)日：2018-03-08

申请号：US15259633

申请日：2016-09-08

Applicant: Qualcomm Technologies, Inc.

Inventor： Stanley Seungchul Song ,  Seong-Ook Jung ,  Hanwool Jeong ,  Giridhar Nallapati ,  Chidi Chidambaram

IPC: H03K3/356 ,  H03K19/096 ,  H03K3/037 ,  H03K3/012

CPC classification number: H03K3/356104 ,  H03K3/012 ,  H03K3/017 ,  H03K3/037 ,  H03K3/0375 ,  H03K19/0963

Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.

公开(公告)号：US10291211B2

公开(公告)日：2019-05-14

申请号：US15259633

申请日：2016-09-08

Applicant: Qualcomm Technologies, Inc. ,  Yonsei University, University-Industry Foundation

Inventor： Stanley Seungchul Song ,  Seong-Ook Jung ,  Hanwool Jeong ,  Tae Woo Oh ,  Giridhar Nallapati ,  Periannan Chidambaram

IPC: H03L7/06 ,  H03K3/356 ,  H03K19/096 ,  H03K3/037 ,  H03K3/012 ,  H03K3/017

Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.