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Patent Agency Ranking
公开(公告)号：US09728259B1
公开(公告)日：2017-08-08
申请号：US15070621
申请日：2016-03-15
Applicant: Qualcomm Technologies, Inc. , Industry-Academic Cooperation Foundation, Yonsei University
Inventor： Seong-Ook Jung , Byung Kyu Song , Taehui Na , Jung Pill Kim , Seung Hyuk Kang
CPC classification number: G11C15/046 , G11C11/1673 , G11C15/02
Abstract: Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin are disclosed. By the NV-CAM cells employing MTJ differential sensing, differential cell voltages can be generated for match and mismatch conditions in response to search operations. The differential cell voltages are amplified to provide a larger match line voltage differential for match and mismatch conditions, thus providing a larger sense margin between match and mismatch conditions. For example, a cross-coupled transistor sense amplifier employing positive feedback may be employed to amplify the differential cell voltages to provide a larger match line voltage differential for match and mismatch conditions. Providing NV-CAM cells that have a larger sense margin can mitigate sensing issues for increased search operation reliability. One non-limiting example of an NV-CAM cell that employs MTJ differential sensing is a ten (10) transistor (10T)-four (4) MTJ (10T-4MTJ) NV-TCAM cell.
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公开(公告)号：US09852783B1
公开(公告)日：2017-12-26
申请号：US15274034
申请日：2016-09-23
Applicant: QUALCOMM TECHNOLOGIES, Inc. , Industry-Academic Cooperation Foundation, Yonsei University
Inventor： Taehui Na , Byung Kyu Song , Seong-Ook Jung , Jung Pill Kim , Seung Hyuk Kang
IPC: G11C11/16
CPC classification number: G11C11/1673 , G11C7/065 , G11C7/08 , G11C11/161 , G11C11/1697 , G11C2207/002 , G11C2207/063
Abstract: Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages are provided. An OCZS-SA is configured to amplify received differential data and reference input voltages with a smaller sense amplifier offset voltage to provide larger sense margin between different storage states of memory bitcell(s). The OCZS-SA is configured to cancel out offset voltages of input and complement input transistors, and keep the input and complement input transistors in their activated state during sensing phases so that sensing is not performed in their “dead zones” when their gate-to-source voltage (Vgs) is below their respective threshold voltages. In other aspects, sense amplifier capacitors are configured to directly store the data and reference input voltages at gates of the input and complement input transistors during voltage capture phases to avoid additional layout area that would otherwise be consumed with additional sensing capacitor circuits.
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公开(公告)号：US10291211B2
公开(公告)日：2019-05-14
申请号：US15259633
申请日：2016-09-08
Inventor： Stanley Seungchul Song , Seong-Ook Jung , Hanwool Jeong , Tae Woo Oh , Giridhar Nallapati , Periannan Chidambaram
Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.
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公开(公告)号：US10224087B1
公开(公告)日：2019-03-05
申请号：US15849863
申请日：2017-12-21
Inventor： Seong-Ook Jung , Sara Choi , Hong Keun Ahn , Seung Hyuk Kang , Sungryul Kim
Abstract: Sensing voltage based on a supplied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations. Sensing voltage based on supply voltage applied to an MRAM bit cell in a write operation can be used to detect completion of magnetic tunnel junction (MTJ) switching in an MRAM bit cell to terminate the write operation to reduce power and write times. In exemplary aspects provided herein, reference and write operation voltages sensed from the MRAM bit cell in response to the write operation are compared to each other to detect completion of MTJ switching of voltage based on the supply voltage applied to the MRAM bit cell regardless of whether the write operation is logic ‘0’ or logic ‘1’ write operation. This provides a higher sensing margin, because the change in MTJ resistance after MTJ switching completion is larger at the supply voltage rail.
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公开(公告)号：US20180069535A1
公开(公告)日：2018-03-08
申请号：US15259633
申请日：2016-09-08
Applicant: Qualcomm Technologies, Inc.
Inventor： Stanley Seungchul Song , Seong-Ook Jung , Hanwool Jeong , Giridhar Nallapati , Chidi Chidambaram
IPC: H03K3/356 , H03K19/096 , H03K3/037 , H03K3/012
CPC classification number: H03K3/356104 , H03K3/012 , H03K3/017 , H03K3/037 , H03K3/0375 , H03K19/0963
Abstract: Adaptive pulse generation circuits for clocking pulse latches with minimum hold time are provided. In one aspect, an adaptive pulse generation circuit employs a dynamic XOR-based logic gate configured to provide a pulse generation signal based on an XOR-based function of data input and data output-based signals of a pulse latch. A pull-down keeper circuit is configured to pull the pulse generation signal to a ground voltage in response to the pulse generation signal being in an inactive state while the clock signal is in an active state. A logic circuit is configured to generate an adaptive pulse signal to clock a pulse latch in response to the pulse generation signal and the clock signal being in an active state. This configuration results in the pulse width of the adaptive pulse signal corresponding to the input-to-output delay of the pulse latch.
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