公开(公告)号：US10854065B1

公开(公告)日：2020-12-01

申请号：US16711148

申请日：2019-12-11

Applicant: Quanta Computer Inc.

Inventor： Kai-Yeh Pan ,  Chun-Ching Yu ,  Hsi-Han Lin ,  Shuen-Hung Wang

IPC: G08B21/18 ,  G01N15/08

Abstract: An electronic device including a housing configured to house one or more electronic components, an air filter, a fan disposed within the housing, and an air pressure sensor disposed within the housing is disclosed. The air filter is disposed within an air inlet defined by the housing. The fan is configured to cause air to enter the housing via the air inlet such that the air flows through the air filter and within the housing. The air pressure sensor generates data used to determine air pressure values within the housing that are based at least in part on the air flowing through the air filter and within the housing. Based on the determined air pressure values from the air pressure sensor, a status of the air filter can be determined, and an indication that the air filter is in need of replacement can be generated and transmitted to a user.

公开(公告)号：US10149401B2

公开(公告)日：2018-12-04

申请号：US14724989

申请日：2015-05-29

Applicant: Quanta Computer Inc.

Inventor： Maw-Zan Jau ,  Chih-Da Wu ,  Shuen-Hung Wang

IPC: G06F13/00 ,  H05K7/14

Abstract: A system includes a rear panel of a housing that includes a first compartment and a second compartment. The system further includes a first module of a first type coupled to the first compartment and a second module of a second type coupled to the second compartment. The first compartment is configured to couple to modules of the first type and the second type, and the second compartment is configured to couple to modules of the first type and the second type.

公开(公告)号：US11269803B1

公开(公告)日：2022-03-08

申请号：US17108733

申请日：2020-12-01

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Shuen-Hung Wang

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40

Abstract: A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.

公开(公告)号：US10533563B2

公开(公告)日：2020-01-14

申请号：US15895360

申请日：2018-02-13

Applicant: QUANTA COMPUTER INC.

Inventor： Chun-Ching Yu ,  Shuen-Hung Wang

IPC: F04D27/00 ,  F04D25/16 ,  G05B15/02

Abstract: The present disclosure provides a system and method for controlling a plurality of cooling fan modules using a management controller and a multiplex switch. The multiplex switch connects the management controller to the plurality of cooling fan modules. The multiplex switch can enable the management controller to select a specific cooling fan module from the plurality of cooling fan modules. Once the specific cooling fan module is selected, the multiplex switch can connect to the specific cooling fan module, enable the management controller to monitor operating characteristics of the specific cooling fan module, and control power or current being delivered to the specific cooling fan module.

公开(公告)号：US11461085B2

公开(公告)日：2022-10-04

申请号：US16294566

申请日：2019-03-06

Applicant: QUANTA COMPUTER INC.

Inventor： Kai-Yeh Pan ,  Chun-Ching Yu ,  Shuen-Hung Wang

IPC: G06F8/65 ,  G06F3/06

Abstract: A multiple storage node system including a first and second node is provided. The first node includes a first baseboard management controller (BMC), a first flash ROM configured to store a first flash image, and a first switch device configured to connect the first BMC to the first flash ROM. The second node includes an exact configuration of the first node. The first BMC is connected to the second switch device, and the second flash image is the same as the first flash.

公开(公告)号：US10929320B1

公开(公告)日：2021-02-23

申请号：US16706330

申请日：2019-12-06

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Shuen-Hung Wang ,  Jui-Chi Huang

IPC: G06F13/20

Abstract: A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.

公开(公告)号：US10806057B2

公开(公告)日：2020-10-13

申请号：US15673031

申请日：2017-08-09

Applicant: QUANTA COMPUTER INC.

Inventor： Shuen-Hung Wang ,  Ting-Chen Ko

IPC: H05K7/20 ,  G06F1/20 ,  G05D23/19 ,  G06F1/26

Abstract: Various examples of the present disclosure provide a multi-node fan control switch and systems and methods for controlling one or more cooling fans of a node using a fan control switch and a specific controller (e.g., BMC or a specific processor) of the node. The node also includes a watch dog circuit. The watch dog circuit can monitor health of the specific controller and, in response to determining that the specific controller has failed, enable the fan control switch to an external mode to allow a controller of a neighboring node in the rack system to control the one or more cooling fans of the node.

公开(公告)号：US10387346B2

公开(公告)日：2019-08-20

申请号：US15149032

申请日：2016-05-06

Applicant: Quanta Computer Inc.

Inventor： Hsiao-Tsu Ni ,  Shuen-Hung Wang ,  Chia-Ju Lee

IPC: G06F13/40 ,  G06F12/02 ,  G06F13/42

Abstract: A system and method for dynamic reconfiguration of at least one peripheral bus switch of a system includes a management controller that detects whether a server system is connected to each peripheral bus slot of the system. The management controller selects a peripheral bus switch topology for the at least one peripheral bus switch, based on the detecting. The management controller sets each port of the at least one peripheral bus switch to either an upstream port configuration or a downstream port configuration, based on the peripheral bus switch topology.

公开(公告)号：US10019402B2

公开(公告)日：2018-07-10

申请号：US15153014

申请日：2016-05-12

Applicant: Quanta Computer Inc.

Inventor： Chun-Chin Yu ,  Shuen-Hung Wang

IPC: G06F13/00 ,  G06F13/40 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0683 ,  G06F11/2092 ,  G06F13/1668 ,  G06F13/387 ,  G06F13/4282

Abstract: In some embodiments, a system for flexible non-volatile memory express drive management can include a first controller including a first drive register and a second drive register, a first processor communicatively coupled with the first drive register via a first serial bus, and a second processor communicatively coupled with the second drive register via a second serial bus. The system can also include a first set of non-volatile memory express drives communicatively coupled with the first processor via the first drive register, and a second set of non-volatile memory express drives communicatively coupled with the second processor via the second drive register and the second serial bus.