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    High Performance, High Capacity Memory Modules and Systems
    2.
    发明申请
    High Performance, High Capacity Memory Modules and Systems 有权

    公开(公告)号：US20230138512A1

    公开(公告)日：2023-05-04

    申请号：US17989838

    申请日：2022-11-18

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

    High Performance, High Capacity Memory Modules and Systems
    4.
    发明申请
    High Performance, High Capacity Memory Modules and Systems 审中-公开

    公开(公告)号：US20180285013A1

    公开(公告)日：2018-10-04

    申请号：US15745396

    申请日：2016-07-14

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS
    6.
    发明申请
    DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS 有权
    用于通信信道的跟踪跟踪反馈

    公开(公告)号：US20150293557A1

    公开(公告)日：2015-10-15

    申请号：US14751312

    申请日：2015-06-26

    Applicant: RAMBUS INC.

    Inventor： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

    IPC: G06F1/08 ,  G06F1/12

    CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14

    Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

    Abstract translation: 一种存储器控制器，具有数据接收器，用于使用选通信号在采样定时采样数据，其中所述数据和所述选通信号由存储器件发送，与由所述存储器控制器发起的读取操作相结合;以及选通接收器，用于接收 所述选通信号，其中所述选通信号的相位相对于参考具有相对于所述量的漂移。 存储器控制器还具有监控电路以监视选通信号并确定漂移量;以及调整电路，用于基于由监视信号确定的漂移量来更新数据接收器的采样定时。

    High performance, high capacity memory modules and systems
    9.
    发明授权
    High performance, high capacity memory modules and systems 有权

    公开(公告)号：US11520508B2

    公开(公告)日：2022-12-06

    申请号：US16880244

    申请日：2020-05-21

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

    High Performance, High Capacity Memory Modules and Systems
    10.
    发明申请
    High Performance, High Capacity Memory Modules and Systems 审中-公开

    公开(公告)号：US20200348870A1

    公开(公告)日：2020-11-05

    申请号：US16880244

    申请日：2020-05-21

    Applicant: Rambus Inc.

    Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

    IPC: G06F3/06 ,  G06F13/16

    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

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