公开(公告)号：US20240380407A1

公开(公告)日：2024-11-14

申请号：US18654022

申请日：2024-05-03

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: H03M1/12 ,  H03M1/44

Abstract: An ADC receives a first input signal and a second input signal and outputs a digital signal. The first input signal is a common-mode voltage plus a voltage difference, and the second input signal is the common-mode voltage minus the voltage difference. The ADC includes a voltage conversion circuit and multiple comparators. The voltage conversion circuit generates an intermediate voltage according to the first input signal, the second input signal, and the common-mode voltage. The comparators compare the intermediate voltage with N times a reference voltage, where N is greater than or equal to negative one and less than or equal to one. The intermediate voltage is the common-mode voltage plus or minus M times the voltage difference, where M is two to the power of R, and R is a positive integer.

公开(公告)号：US20230308110A1

公开(公告)日：2023-09-28

申请号：US18119311

申请日：2023-03-09

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG ,  WEI-CIAN HONG

IPC: H03M1/46

CPC classification number: H03M1/466 ,  H03H19/004

Abstract: A comparator-based switched-capacitor circuit has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and includes an analog-to-digital converter (ADC), a decoder, and a switch-capacitor network. The ADC is coupled to the first input terminal and the second input terminal and includes a plurality of comparators. The decoder is coupled to the ADC. The switch-capacitor network includes a comparator, a first current source, a second current source, a plurality of switches, and a plurality of capacitors. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The voltage of the first output terminal and the voltage of the second output terminal do not exceed a target range.

公开(公告)号：US20230308105A1

公开(公告)日：2023-09-28

申请号：US18087469

申请日：2022-12-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： HSUAN-TING HO ,  SHIH-HSIUNG HUANG ,  LIANG-WEI HUANG

IPC: H03M1/06 ,  G01K7/00

CPC classification number: H03M1/0607 ,  G01K7/00

Abstract: The present invention discloses a digital-to-analog conversion apparatus having current source measuring mechanism. A digital-to-analog conversion circuit in turn sets one of thermo-controlled current sources as an initial current source to operate according to two specific input codewords included in an input digital signal to generate an output analog signal. The values of the output analog signal corresponding to the two specific input codewords have opposite signs and the same absolute value. An echo transmission circuit processes the output analog signal to generate an echo signal. An echo-canceling circuit processes the input digital signal according to echo-canceling coefficients to generate an echo-canceling signal and receives an error signal to converge the echo-canceling coefficients. A current calculating circuit generates converged coefficients statistics values and perform calculation thereon with a predetermined inverse matrix to generate a current amount of each of the thermo-controlled current sources. An error calculation circuit subtracts the echo signal and the echo-canceling signal to generate the error signal.

公开(公告)号：US20230184816A1

公开(公告)日：2023-06-15

申请号：US17973039

申请日：2022-10-25

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: G01R19/165 ,  G01R19/00 ,  H03K5/24

CPC classification number: G01R19/16576 ,  G01R19/0038 ,  H03K5/249

Abstract: The present invention discloses a comparison circuit having adaptive comparison mechanism is provided. A comparator is enabled by an enabling signal having an enabling state during a comparison stage to compare a first voltage and a second voltage to generate a comparison result. A comparison determining circuit sets a stage indication signal at an unfinished state and a finished state before and after the comparison result is generated. A time accumulating circuit starts to accumulate an accumulated time when the enabling signal is at the enabling state and stops accumulating when the stage indication signal is at the finished state to generate a comparison time. A determining circuit performs statistics on the comparison time to generate a predetermined threshold time and sets a predetermined comparison result as the comparison result under the condition that the comparison result is not generated and the accumulated time exceeds the predetermined threshold time.

公开(公告)号：US20230140965A1

公开(公告)日：2023-05-11

申请号：US17864471

申请日：2022-07-14

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG ,  YEN-TING WU ,  WEI-CIAN HONG

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/1215

Abstract: A front-end sampling circuit includes a global switch, a local switch, and an auxiliary switch. The global switch is configured to be selectively turned on according to a first control signal, in order to transmit an input signal. The local switch is configured to be selectively turned on according to a second control signal, in order to transmit the input signal from the global switch to a node, wherein a storage circuit is coupled to the node to store the input signal. The auxiliary switch is configured to be selectively turned on according to a third control signal, in order to transmit the input signal to the node, in which a turn-off time point of the auxiliary switch is set to be the same or earlier than a turn-off time point of the global switch.

公开(公告)号：US20230116785A1

公开(公告)日：2023-04-13

申请号：US17870958

申请日：2022-07-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： JUN YANG ,  SHIH-HSIUNG HUANG ,  YEN-TING WU

IPC: H03M1/46 ,  H03M1/12

Abstract: A successive approximation register analog to digital converter device includes first and second digital to analog converter (DAC) circuits, a comparator circuit, a controller circuit, and a dynamic element matching (DEM) circuit. The first and second DAC circuits samples an input signal. The comparator circuit and the controller circuit generate first and second bits according to outputs of the first and second DAC circuits. The DEM circuit encodes the first bits to generate third bits, in order to refresh the first DAC circuit. After the first DAC circuit is refreshed, the controller circuit resets partial bits in the second bits. After the partial bits are reset, the comparator circuit generates comparison results according to outputs of the first and second DAC circuits. The controller circuit generates fourth bits according to the comparison results, and generates a digital output according to the first, second, and fourth bits.

公开(公告)号：US20220367447A1

公开(公告)日：2022-11-17

申请号：US17676852

申请日：2022-02-22

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: H01L27/08 ,  H01L23/50 ,  H01L23/482 ,  H01L49/02

Abstract: A finger-type semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral power supply strips. The second conductive structure includes longitudinal second conductive strips and P lateral power supply strip(s). The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit (IC) layer; and the longitudinal first conductive strips include a first row of strips and a second row of strips. The lateral power supply strips are located in a second IC layer, and coupled to the first and second rows of strips through vias. The P lateral power supply strip(s) is/are located in the second IC layer, and include(s) a first-capacitor-group power supply strip that is coupled to K strip(s) of the longitudinal second conductive strips through K via(s). The P and K are positive integers.

公开(公告)号：US20220158648A1

公开(公告)日：2022-05-19

申请号：US17408524

申请日：2021-08-23

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: H03M1/12 ,  H03M1/46

Abstract: A pipeline analog to digital converter includes converter circuitries. The converter circuitries are configured to sequentially convert an input signal to be digital codes. The converter circuitries includes a first converter circuitry and a second converter circuitry. The first converter circuitry is configured to a convert a first signal to be a first digital code in the digital codes, and generate a first residue signal according to the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code to quantize the first signal according to the first digital code, in order to generate a second digital code in the digital codes, and generate a second residue signal according to the first residue signal and the second digital code.

公开(公告)号：US20210203347A1

公开(公告)日：2021-07-01

申请号：US17096989

申请日：2020-11-13

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： WEI-CHOU WANG ,  CHIH-CHIEN CHANG ,  SHIH-HSIUNG HUANG

IPC: H03M1/44 ,  H03M1/46

Abstract: A multi-stage switched capacitor circuit and an operation method thereof are provided. The multi-stage switched capacitor circuit includes a first operational stage, a second operational stage and a third operational stage that are serially connected in order. Each operational stage operates in a sample phase or a hold phase and generates a detection signal indicating an end of the hold phase. The operation method of the multi-stage switched capacitor circuit includes: controlling the second operational stage to operate in the hold phase when the detection signal of the first operational stage indicates the end of the hold phase of the first operational stage, and the detection signal of the third operational stage indicates the end of the hold phase of the third operational stage.

公开(公告)号：US20210105014A1

公开(公告)日：2021-04-08

申请号：US17062813

申请日：2020-10-05

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： SHIH-HSIUNG HUANG

IPC: H03K19/017 ,  H03K17/06 ,  H03K19/096

Abstract: A bootstrapped switch is provided. The bootstrapped switch includes a first transistor, a second transistor, a capacitor and five switches. The first transistor receives an input voltage and outputs an output voltage. A first terminal of the second transistor receives the input voltage, and a second terminal of the second transistor is coupled to a first terminal of the capacitor. In a first clock phase, the capacitor is being charged. In a second clock phase, the control terminal of the first transistor and the control terminal of the second transistor are substantially equipotential with a second terminal of the capacitor. The control terminal of the first transistor and the control terminal of the second transistor are coupled to the power supply voltage within a predetermined time before the terminal of the first clock phase or within a predetermined time after the start of the second clock phase.