Circuit layout of printed circuit board
    1.
    发明公开

    公开(公告)号:US20240349421A1

    公开(公告)日:2024-10-17

    申请号:US18415699

    申请日:2024-01-18

    Abstract: A layout without bridge taps includes: a routing from a CPU to a first module through a first set of pads; a routing from a first set of bridge pads to a second module through a second set of pads and a second set of bridge pads; a routing from a third set of pads to a third module; and connectors. The connectors connect pads of the first set of pads to couple the CPU with the first module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the second set of bridge pads to couple the CPU with the second module, or connect the first set of pads with the first set of bridge pads and connect the second set of pads with the third set of pads to couple the CPU with the third module.

    Power failure detection device and method

    公开(公告)号:US11704991B2

    公开(公告)日:2023-07-18

    申请号:US17316750

    申请日:2021-05-11

    CPC classification number: G08B21/185 G01R19/1659 G08B21/182 H02J9/061

    Abstract: Disclosed is a power failure detection device and method capable of issuing a power failure alert early. The device includes a voltage reduction circuit, a detection voltage generating circuit, a detection circuit, and a transmitting circuit. The voltage reduction circuit is or includes at least one active electronic component, and generates an output voltage according to an input voltage higher than the output voltage. The detection voltage generating circuit is coupled between the voltage reduction circuit and a low voltage terminal, and generates a detection voltage according to the output voltage that is between the output voltage and the voltage of the low voltage terminal. The detection circuit generates a detection result according to the detection voltage and a trigger voltage. The transmitting circuit sends a power failure alert to a far-end device on condition that the detection result indicates that the detection voltage is lower than the trigger voltage.

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