公开(公告)号：US20240170373A1

公开(公告)日：2024-05-23

申请号：US18483740

申请日：2023-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hideaki TAMIMOTO ,  Masatoshi SUGIURA ,  Atsushi SAKAZAKI

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49513 ,  H01L21/4828 ,  H01L21/4842 ,  H01L23/49548 ,  H01L23/49582 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L23/3121 ,  H01L23/49568 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48247 ,  H01L2224/49111

Abstract: An upper surface of a main portion of a die pad includes a first region overlapping a semiconductor chip, a second region arranged between a side and the first region, and a third region arranged between the first region and a connecting portion. In the upper surface of the main portion, each of a second trench length of a second trench arranged in the second region and a third trench length of a third trench arranged in the third region is larger than a first trench length of a first trench arranged in the connecting portion. Each of a second trench width of the second trench arranged in the second region and a third trench width of the third trench arranged in the third region is smaller than a first trench width of the first trench arranged in the connecting portion.