公开(公告)号：US20180068712A1

公开(公告)日：2018-03-08

申请号：US15799073

申请日：2017-10-31

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  H01L27/11 ,  H01L29/10 ,  H01L23/528

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

公开(公告)号：US09837140B2

公开(公告)日：2017-12-05

申请号：US15389192

申请日：2016-12-22

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C5/14 ,  G11C11/417 ,  H01L27/11 ,  H01L29/10 ,  H01L23/528

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device including a first N-type well and a second N-type well includes: a memory circuit to be coupled with first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line and electrically decouples the first power source line from the second power source line. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The first and second switches each include a first PMOS transistor arranged in the first N-type well.

公开(公告)号：US10482949B2

公开(公告)日：2019-11-19

申请号：US16272123

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C5/14 ,  G11C11/417 ,  H03K19/00 ,  H03K17/687 ,  H01L23/528 ,  H01L27/11 ,  H01L29/10

Abstract: A semiconductor device includes a first mode and a second mode different from the first mode, includes a memory circuit including a first switch, a memory array, and a peripheral circuit. A first power source line is electrically coupled with an I/O circuit of the peripheral circuit and is supplied with a first voltage in the first mode. A second power source line is electrically coupled with a memory cell of the memory array, and supplied with a second voltage lower than the first voltage in the second mode.

公开(公告)号：US10446224B2

公开(公告)日：2019-10-15

申请号：US15887190

申请日：2018-02-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  G11C5/14

Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

公开(公告)号：US09959925B2

公开(公告)日：2018-05-01

申请号：US15799073

申请日：2017-10-31

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C5/14 ,  G11C11/417 ,  H01L27/11 ,  H01L23/528 ,  H01L29/10

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device including an active mode and a standby mode as operation modes, includes: a first power source line which accepts the supply of power in the active mode; a second power source line which accepts the supply of power in the active mode and the standby mode; a memory circuit to be coupled with the first and second power source lines; and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array to be coupled with the second power source line, a peripheral circuit to be coupled with the first power source line, and a second switch which electrically couples the first power source line with the second power source line.

公开(公告)号：US09922698B2

公开(公告)日：2018-03-20

申请号：US14484998

申请日：2014-09-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Kenichi Osada ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  G11C5/14

CPC classification number: G11C11/417 ,  G11C5/14 ,  G11C5/148

Abstract: A semiconductor integrated circuit device has a memory array including SRAM cells, a plurality of sense amplifiers for reading out data stored in the SRAM cells and a plurality of MOSFETS. The MOSFETs are controlled by a control signal to be in one of an active state or a standby state. Part of the MOSFETs are arranged along one end of the memory array and the other parts of the MOSFETs are arranged along another end of the memory array. The other end of the memory array is opposite to the one end of the memory array. The MOSFETs are controlled by the control signal to be turned ON in the active state and to be turned OFF in the standby mode.

公开(公告)号：US20130169247A1

公开(公告)日：2013-07-04

申请号：US13674766

申请日：2012-11-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masafumi Onouchi ,  Kazuo Otsuga ,  Yasuto Igarashi ,  Sadayuki Morita ,  Koichiro Ishibashi ,  Kazumasa Yanagisawa

IPC: G05F1/59

CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

公开(公告)号：US10224096B2

公开(公告)日：2019-03-05

申请号：US15921226

申请日：2018-03-14

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C5/14 ,  G11C11/417 ,  H03K19/00 ,  H03K17/687 ,  H01L23/528 ,  H01L27/11 ,  H01L29/10

Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

公开(公告)号：US20180204612A1

公开(公告)日：2018-07-19

申请号：US15921226

申请日：2018-03-14

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: G11C11/417 ,  H01L29/10 ,  H01L23/528 ,  H01L27/11

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device includes: a first power source line for supplying a first voltage; a second power source line for supplying a second voltage; a memory circuit coupled with the first and second power source lines; a first switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to a control signal; a second switch which electrically coupling the first power source line with the second power source line and electrically decoupling the first power source line from the second power source line, in response to the control signal, wherein a memory circuit includes a memory cell array and a peripheral circuit, wherein a memory cell array includes a plurality of memory cells, the memory cells coupled with the second power source line.

公开(公告)号：US09559693B2

公开(公告)日：2017-01-31

申请号：US14866544

申请日：2015-09-25

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro Ishii ,  Atsushi Miyanishi ,  Kazumasa Yanagisawa

IPC: H03K19/00 ,  H03K17/687

CPC classification number: G11C11/417 ,  H01L23/5286 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/1095 ,  H03K17/6871 ,  H03K19/0016

Abstract: A semiconductor device includes a first power source line which accepts the supply of power in the active mode, a second power source line which accepts the supply of power in the active mode and the standby mode, a memory circuit to be coupled with the first and second power source lines and a first switch which electrically couples the first power source line with the second power source line in the active mode and electrically decouples the first power source line from the second power source line in the standby mode. The memory circuit includes a memory array, a peripheral circuit and a second switch. Each of the first and second switches includes a first PMOS transistor and a second PMOS transistor.

Abstract translation: 一种半导体器件包括接受主动模式下的电力供给的第一电源线，接受主动模式和备用模式的电力供给的第二电源线，与第一和第二电力线耦合的存储电路， 第二电源线和第一开关，其将第一电源线与第二电源线以活动模式电耦合，并且在待机模式下将第一电源线与第二电源线电耦合。 存储器电路包括存储器阵列，外围电路和第二开关。 第一和第二开关中的每一个包括第一PMOS晶体管和第二PMOS晶体管。