公开(公告)号：US09672872B2

公开(公告)日：2017-06-06

申请号：US15190263

申请日：2016-06-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada Funane ,  Ken Shibata ,  Yasuhisa Shimazaki

IPC: G11C5/02 ,  G11C5/06 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US10566047B2

公开(公告)日：2020-02-18

申请号：US16250275

申请日：2019-01-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada Funane ,  Ken Shibata ,  Yasuhisa Shimazaki

IPC: G11C5/02 ,  G11C11/417 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/02 ,  H01L27/11 ,  G11C5/06

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US09978445B2

公开(公告)日：2018-05-22

申请号：US15373783

申请日：2016-12-09

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US10224095B2

公开(公告)日：2019-03-05

申请号：US15795502

申请日：2017-10-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada Funane ,  Ken Shibata ,  Yasuhisa Shimazaki

IPC: G11C5/02 ,  G11C11/417 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/02 ,  H01L27/11 ,  G11C5/06

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US09548106B2

公开(公告)日：2017-01-17

申请号：US15134981

申请日：2016-04-21

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。

公开(公告)号：US09378773B2

公开(公告)日：2016-06-28

申请号：US14490235

申请日：2014-09-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada Funane ,  Ken Shibata ,  Yasuhisa Shimazaki

IPC: G11C5/02 ,  G11C7/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US10510400B2

公开(公告)日：2019-12-17

申请号：US15957263

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/16 ,  G11C11/412

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US09865604B2

公开(公告)日：2018-01-09

申请号：US15277723

申请日：2016-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken Shibata ,  Yuta Yanagitani

IPC: H01L29/66 ,  H01L27/11 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1116 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42356

Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

公开(公告)号：US09830975B2

公开(公告)日：2017-11-28

申请号：US15583093

申请日：2017-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kiyotada Funane ,  Ken Shibata ,  Yasuhisa Shimazaki

IPC: G11C5/02 ,  G11C11/417 ,  G11C8/16 ,  G11C7/10 ,  G11C11/412

CPC classification number: G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

公开(公告)号：US09478554B2

公开(公告)日：2016-10-25

申请号：US14990262

申请日：2016-01-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Ken Shibata ,  Yuta Yanagitani

IPC: H01L21/84 ,  H01L27/11 ,  H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  G11C11/412 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419

CPC classification number: H01L27/1104 ,  G11C5/14 ,  G11C11/412 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419 ,  H01L21/823892 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1116 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/42356

Abstract: A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are alternately arranged to be adjacent to each other along an X-axis direction. A common power feeding region (ARP2) for the plurality of wells PW is arranged on one side so as to interpose the AR1 in a Y-axis direction, and a common power feeding region (ARN2) for the plurality of wells NW is arranged on the other side. In the power feeding region (ARP2) for the PW wells, a p+-type power-feeding diffusion layer P+(DFW) having an elongate shape extending in the X-axis direction is formed. A plurality of gate layers GT extending in the X-axis direction to cross the boundary between the PW and NW wells are arranged in the AR1, and a plurality of MIS transistors are correspondingly formed.

Abstract translation: 具有高自由度布置的半导体器件具有第一部分AR1，其中多个p型阱PW和n型阱NW沿着X轴方向交替布置成彼此相邻。 多个井PW的公共供电区域（ARP2）布置在一侧，以将AR1插入Y轴方向，并且用于多个井NW的公共供电区域（ARN2）布置在 另一边。 在PW阱的供电区域（ARP2）中，形成具有沿X轴方向延伸的细长形状的p +型供电扩散层P +（DFW）。 在AR1中布置有沿X轴方向延伸以跨越PW和NW阱之间的边界的多个栅极层GT，并且相应地形成多个MIS晶体管。